Abstract: An emulator controls two single port memories by switching to exclusively connect the single port memories to a target microcomputer and a control microcomputer.

Abstract: A data processor in an image coding apparatus includes a zero detecting circuit for determining if the quantized AC coefficients are zero or not; a counter, that is reset periodically, for counting the quantized AC coefficients that are not zero; a comparator for comparing the count of the counter and a first reference value, and outputting an AC coefficient eliminating signal when the count exceeds the first reference value; and a first logic circuit for forcibly replacing the quantized AC coefficients with zero based on the AC coefficient eliminating signal so that the volume of data of the quantized AC coefficients that are not zero is reduced. The image coding apparatus cuts off some portions for the images having a large volume of codings, and keeps the volume of data below a predetermined maximum.

Abstract: An emulation apparatus is connected to a host computer and a target system for verifying the operation of a program written for the target system. A microcomputer in the emulation apparatus executes the program written for the target system. In an undo mode, the execution of a program is halted at the end of the execution of each instruction. At that time, information on relative bus cycles is stored in a relative-bus cycle area of a memory. The contents of data and control registers in a target system are acquired and stored in data-register and control-register areas.

Abstract: A D flip-flop latches a reference clock signal in response to an output signal fed back from an output circuit. A pulse generating circuit generates a pulse in response to the output signal fedback from the output circuit. From the latched signal and the pulse generated by the pulse generating circuit, a count pulse is generated. The count pulse is output to an up/down counter. Based on the counting result of the up/down counter, a digital-to-analog conversion circuit generates a delay control signal. Using this delay control signal, the delay circuit synchronizes its output signal with the reference clock signal. It is possible to synchronize the output data signal with the reference clock signal regardless of variations in the reference clock signal, source voltage, and ambient temperature.

Abstract: A microcomputer includes a central processing unit for sequentially executing instructions according to a software program. When the CPU decodes a marker, the CPU determines the location of the marker within the software program and produces a marker decoding signal showing that the CPU has decoded the marker. A monitor unit obtains CPU operation information about operation of the CPU in response to the marker decoding signal. The monitor unit provides to a storage unit the CPU operation information and a marker identifier showing that the marker has been decoded.

Abstract: An IC card having a memory for receiving data from and sending data to a data reader/writer includes a reading-completion detection circuit for detecting if each sense amplifier in the IC card has completed data reading from the memory and a control circuit which ignores a command sent from the data reader/writer when no reading completion detection signal is output from the data reading-completion detection circuit upon verifying a password sent from the data reader/writer.

Abstract: A power switching circuit solves a problem associated with conventional power switching circuits. It has been difficult to achieve positive power switching for the operation of low threshold transistors using a voltage below the forward voltage drop of a diode. The difficulty arose because the P-channel transistors on the unselected side of the power switching circuit could not be cut off completely. A power switching circuit according to the present invention includes a power switching portion and a level shifter. The power switching portion includes a first series circuit of two P-channel transistors connected in series across a first input terminal and an output terminal. A second series circuit of two P-channel transistors connected in series is connected across a second input terminal and the output terminal. A level shifter brings the first series circuit into conduction and takes the second series circuit out of conduction in response to the control signal.

Abstract: In a timer apparatus, the clock controlling circuit thereof outputs a clock signal during a period in which an input signal is significant. The counter thereof counts the number of pulses of the clock signal to generate a count-up signal when the value of count reaches a prescribed value. The initialization circuit thereof outputs an initialization signal when the input is not significant. The clock controlling circuit stops the output of the clock signal when the count-up signal is generated. Thereby, it is prevented to misjudge the detection of an effective pulse width to achieve the effective pulse width though the pulse width of the pulse does not actually reach the effective pulse width actually.

Abstract: A communications device, such as a non-contact IC card, demodulates a received carrier signal, which has been modulated with data to be transmitted thereto by changing the phase of the carrier signal intermittently according to the data, so as to extract the data from the carrier signal.

Abstract: An interface apparatus, built in a microcomputer, and capable of reducing the load on a CPIU by including a function to judge by itself, when data is received from the outside, whether it is necessary for the received data to generate an interruption request so as to make the (CPU execute the processing, thereby avoiding the generation of an unnecessary interruption request. The interface apparatus is provided with a receiving register 3 which stores data received newly, a buffer register 4 which stores data received precedingly, a table 5 which stores data designated beforehand, and a comparing circuit 6 which compares the data stored in them with each other to make an interruption control register 7 generate an interruption request signal INT only when the comparison results do not show coincidence.

Abstract: A semiconductor integrated circuit device includes a high density cell in which a more densely integrated layout is provided by combining cells having the same circuit configuration and sharing a basic gate portion among each of the cells.

Abstract: An emulator apparatus includes an access information memory in which, when an emulation program makes a write access to a memory address of a microcomputer, and information showing the presence of the write access is related to the write-accessed address and is stored. A break circuit to break execution of the emulation program when the emulation program makes a read access to the memory address of the microcomputer is provided, and the access information memory does not contain information showing the presence of the write access to the read-accessed address.

Abstract: An antenna mechanism for a noncontacting IC card system for communication with a noncontacting IC card passing a gate, the antenna mechanism including an antenna; and a conductive shielding body located on an outer side of the gate to eliminate a communication area outside the gate by shielding electromagnetic waves from the antenna.

Abstract: A semiconductor circuit logical check apparatus including a unit for extracting information about laser trimming fuse elements based on layout data and logic-circuit diagram data of a semiconductor circuit, a unit for generating a command sequence indicating that some of the laser trimming fuse elements are broken on the basis of the extracted laser trimming fuse element information, a unit for generating error bit memory cell array models from memory cell array models, and a unit for executing, on a semiconductor circuit model, logic simulation on the basis of the command sequence.

Abstract: A non-contact IC card reader/writer which offers an improved reliability in communication between a non-contact IC card and its reader/writer by reducing malfunction due to data communication error. The reader/writer includes a reader/writer main body electrically connected to a host machine for controlling communications, and an antenna external to and electrically connected to the reader/writer main body for transmitting and receiving electromagnetic waves to and from the non-contact IC card. Since the antenna is L-shaped in cross section, the non-contact IC card is free from right-angle antenna geometry to the antenna and maintains a good communications link with the reader/writer.

Abstract: According to the present invention, when a semiconductor device is tested, a signal for test can be set in the semiconductor device at a desired timing. A second delay circuit of the present invention has the same structure as a first delay circuit in a phase lock loop, and receives a control voltage from the phase lock loop so as to generate a clock signal with a frequency according to the control voltage and to delay and output the clock signal. A second pulse generator generates two-phase clocks by using delayed signals generated by the second delay circuit. Switches are used for switching between a system clock output terminal during an actually active time and a system clock output terminal during testing.

Abstract: A non-contact type IC card comprising a memory including a manufacturer code area and an error signal output circuit is disclosed. The error signal output circuit outputs an error signal such that an access from a read/write apparatus is allowed when a password coincidence is obtained when a predetermined code is stored in the manufacture code area. On the other hand, when the predetermined code is not stored in the manufacturer code area, the error signal output circuit outputs an error signal such that an access to all the memory area from the read/write apparatus is allowed regardless of a result of the password collation performed by the password collation circuit.

Abstract: A print controlling apparatus includes a printing head with columns of printing elements. A buffer circuit includes data storage columns corresponding to the printing element columns on the printing head. The buffer circuit also includes data storage columns corresponding to a printing region between the printing element columns on the printing head. Printing data is transferred from the data storage columns in the buffer circuit corresponding to the printing element columns on the printing head. After the data is transferred from the data storage columns to the printing head, a shift controlling circuit shifts printing data in the data storage columns corresponding to the intermediate region to the data storage columns corresponding to the printing element columns on the printing head. By storing and shifting data from the data storage columns corresponding to the printing region between the printing element columns on the printing head, processing time during a print cycle is reduced.

Abstract: A storage portion places data through a data output buffer on a data line D0.sub.P when a control line R00H becomes active, and places data through a data output buffer on a data line D0.sub.Q when a control line R03H becomes active. The storage portion further takes as input a signal on the data line D0.sub.P through a transmission gate when a control line W00H becomes active, and takes as input a signal on the data line D0.sub.Q through a transmission gate when a control line W003H becomes active. Thus, a storage device is provided to have the storage portion accessed by a plurality of access means at different addresses. It is thereby possible to select the optimal method of access to the storage portion, resulting in prevention of reduction of a program efficiency.

Abstract: An emulator probe comprising a plurality of upper connectors fixed to the upper surface of a direction changing board, the upper connectors having terminals electrically connected to the terminals of a lower connector, the upper connectors being fixed to the upper surface with different fixing angles to each other, whereby an emulator can be mounted on a user target board without deforming an emulator cable.