Abstract: In a switch level simulation system of the present invention, bidirectional switch models are allocated more accurately at locations which need to be bidirectional in circuit connection information and uni-directional switch models corresponding to the flow direction of a signal are allocated at the other locations. The connection information extracting section extracts the connection state of each device in a circuit indicated by circuit information and produces connection information. The input/output type determining section determines whether or not a switching device in a circuit is bidirectional and the flow direction of a signal in a uni-directional switching device, according to connection information. The circuit connection information generating section generates circuit connection information to be used by a simulation executing section, using the result of determining of the input/output type determining section.

Abstract: In a semiconductor circuit design verifying apparatus, a parasitic device retrieving part retrieves a parasitic device for a signal line connecting first stage active devices to a next stage active device. A time constant computing device computes a time constant between each first stage active device and the next stage active device including the parasitic device for the signal line between the first stage active devices and the next stage active device. An output data generating device outputs the time constant and information associated with the time constant to a user.

Abstract: In an IC card, a user area is set to have a first area in which a write password is made valid, and a second area in which a read password is made valid. When a write command for the first area is sent together with a password from a read/write apparatus, the password is collated with the write password. When a read command for the second area is sent together with a password, the password is collated with the read password. As a result of the collation, when the passwords are identical, the respective commands are executed.

Abstract: A microcomputer including an EEPROM in which data may be stored and from which stored data may be read either under control of a central processing unit of the microcomputer or under direct external control. The microcomputer includes separate inputs for data input and data output signals when storing and reading is under the control of the central processing unit and when storing and reading of data is under direct external control. The central processing unit may inhibit direct external control of storing data in and reading data from the EEPROM.

Abstract: An A/D converter wherein data obtained by A/D converting an analog signal in an A/D converting unit is stored in a first register, the data in the first register and the data in a second register are compared to each other by a comparator, and when the data in the first register is larger (or smaller) than that in the second register, a first switching means is closed so that the data in the first register is stored in the second register. In the second register, a maximum value (or a minimum value) of the A/D-converted data hitherto obtained is stored.

Abstract: An analog-to-digital converter includes a comparator for comparing a voltage output by a digital-to-analog converter with an input analog voltage at each bit of an n-bit word. The input analog voltage and the analog output voltage of the digital-to-analog converter are alternatingly used as the reference in the comparison, i.e., for every other bit of the n bits. A one-bit result-of-comparison signal indicative of the result of the comparison is output for each of the n bits. Only alternating result-of-comparison signals are inverted and the inverted and non-inverted result-of-comparison signals are stored in a successive approximation register as the converted digital signal and are supplied to the digital-to-analog converter for use in the comparison.

Abstract: A microcomputer comprising an exclusive register 61, an STP/WIT instruction valid/invalid control circuit 60 which detects that data are written consecutively in the register 61 and that values of the data are in a predetermined combination, and AND gates 11 and 12 which permit execution of the STP instruction and the WIT instruction for stopping clock .phi. only when the predetermined signal is outputted from the STP/WIT instruction valid/invalid control circuit 60, and capable of avoiding the instruction for stopping the internal clock being executed by mistake.

Abstract: A analog-to-digital converting device includes an analog-to-digital converting operation control unit for temporarily stopping an analog-to-digital converter in response to a trigger signal applied thereto and for restarting the analog-to-digital converter by imposing the operation conditions, which have been initially set up, on the analog-to-digital converter again. The device can forcefully terminate a scanning operation and restart analog-to-digital converting operations in a scan mode under the initially set up operating conditions without having to use an interrupt program executed by a CPU.

Abstract: A noncontacting IC card system occupying a relatively small area without requiring a provision for a dead zone or unnecessary communication area outside a gate. A transmitting antenna 11 is provided between two contiguous gates i.e., on the inner sides of the gates, and receiving antennas are provided respectively toward the sides opposite to the transmitting antenna of the gates i.e., on the outer sides of the gates. It is thereby not necessary to provide a dead zone between the gates and an unnecessary communication area does not occur outside the gate.

Abstract: A single-chip microprocessor with a self-testing function for quickly detecting internal errors or defects while mounted to a circuit board without adversely affecting any external electronic devices connected thereto.A single-chip microprocessor comprising a built-in self-testing function for testing the internal circuitry thereof comprises a test mode signal output means for outputting the test mode signal when in the test mode, which is a mode for self-diagnostic testing of the internal circuitry; and an external output holding means disposed to the external output means for outputting signals from an external output terminal, and holding the output signal status of the external output terminal while the test mode signal is input from the test mode signal output means; and testing the internal circuitry of the single-chip microprocessor while holding the output signal status of the external output terminal.

Abstract: A microcomputer has a timer register 10 for storing period data of a carrier, timer registers 4A and 4B for individually storing positive phase and negative phase time width data of a control signal which is synchronized with the carrier, and an operation unit 13 for subtracting the value of the positive phase time width data of the control signal from a value of the period data. The time width data obtained as a subtraction result is supplied to the timer register 4B. The load on the CPU when the revolution of an induction motor is controlled is reduced.

Abstract: An in-circuit emulator comprises a pod portion mounted with a microcomputer equivalent to a target microcomputer and an emulator main body which offers a debug function. There are provided between the pod portion and the emulator main body a common bus to be connected either to a bus of a controlling microcomputer in the emulator main body or to a bus of a microcomputer in the pod portion and a serial input-output line for realizing information exchange between the controlling microcomputer and the pod portion.

Abstract: A semiconductor memory device pre-charges the electric potential of a selected bit line up to a predetermined electric potential, and judges the electric potential of the selected bit line on the basis of the predetermined electric potential as a threshold value after the pre-charge. Thereby, a semiconductor memory device capable of being read out at high speed can be realized.

Abstract: A microcomputer or a one-chip computer has address pins and data pins provided separately, and when a specified control signal is provided, the address pins act as multiplex pins for address and data signals. Further, a combination of bits for address signals and bits for data signals to be provided to the multiplex pins are changed according to a width of an external bus. For example, the data bits D.sub.i are combined with the address bits A.sub.i, as used previously. Further, the data bits D.sub.i-1 are combined with the address bits A.sub.i by shifting by one bit with respect to the address bits. One of the two types of the combination can be selected. If the microcomputer has 16-bit address pins, it can be connected to 8-bit memories having independent address and data pins, while it can also be connected to 8-bit peripherals having multiplex pins without using an external circuit for separating address and data signals.

Abstract: Addresses for a plurality of consecutive logic blocks are managed by assigning the addresses to their corresponding addresses for physical blocks of a plurality of flash memory devices such that the addresses for the plurality of continuous logic blocks are respectively distributed into the plurality of flash memory devices. When block erase commands are inputted from the outside, chip enable signals are respectively transmitted to at least two of the flash memory devices in which physical blocks to be erased exist, in such a manner that a period in which at least two flash memory devices simultaneously perform block erase operations, exists.

Abstract: An analog/digital (A/D) converter includes a sequential approximation register (SA register) having a plurality of bits for storing the results of conversion in digits and an incrementor having a smaller number of bits than that of the SA register. The incrementor increments a portion of the results of conversion on the basis of the result of conversion of at least one bit in the SA register so as to minimize an error in the A/D conversion of a smaller number of bits than that of the SA register.

Abstract: Even in the case where a microcomputer according to the present invention is directly connected to a bus in a LAN, it is possible to upgrade the data transfer speed of the LAN. When a built-in exclusive-OR circuit in the SIO of the microcomputer detects the discordance between a signal at an R.times.D terminal and a signal at a T.times.D terminal, a D flip-flop circuit generates and sends out an interrupt signal to the CPU. The CPU is made to recognize the collision of signals by the generation of the interrupt signal.

Abstract: A microcomputer comprising a clock circuit which selects a pulse signal as a system clock of the microcomputer from among a plurality of pulse signals and a power source impedance controlling circuit which controls an impedance between a power input terminal and the units of the microcomputer based on the frequency of the pulse signal selected by the clock circuit to provide the electric power to the units of the microcomputer. The power source impedance controlling circuit controls the impedance such that the power source impedance is made lower as the frequency of the selected pulse signal is higher.

Abstract: A digital/analog converting circuit wherein, on the digital signal input side of each of resistances D.sub.1, D.sub.2 . . . D.sub.n whose one end being connected to a digital signal input and the other end to an analog signal output, each of the three-state non-inverting buffers B.sub.1, B.sub.2 . . . B.sub.n is provided, and between the analog signal output side of the resistance D.sub.n and the ground potential portion, a MOS transistor 20 is provided. It enables to switch the output/non-output or an analog signal obtained by converting a digital signal, and as a result, a digital/analog converting circuit not generating non-linear region in the digital/analog conversion characteristic can be obtained.

Abstract: A sense amplifier circuit comprising a capacitor 12 having a capacity larger than a parasitic capacity 32 of a selected bit line 33, and a differential amplifier 30 for fixing, after the determination of the read data, the voltage level of the selected bit line to a level at which a read current does not flow through said selected bit line, or for cutting a quasi-write in current so as not to be flown into the selected memory cell, thereby the consuming current is reduced and damage of data due to quasi write in is prevented.