Patents Assigned to Monolithic 3D Inc.
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Publication number: 20200335399Abstract: A 3D semiconductor device including: a first level including first single crystal silicon and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors; a second level on top of the first metal layer, the second level including a plurality of second transistors; a third level on top of the second level, the third level including a plurality of third transistors; an oxide layer on top of the third level; a fourth level on top of the oxide layer, the fourth level including second single crystal silicon and many fourth transistors, where at least one of the plurality of second transistors is at least partially self-aligned to at least one of the plurality of third transistors, both being formed following the same lithography step, the fourth level is bonded to the oxide layer, the bonded includes many metal to metal bonded structures.Type: ApplicationFiled: June 29, 2020Publication date: October 22, 2020Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Publication number: 20200321285Abstract: A 3D semiconductor device and structure, the device including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, where second die includes an array of memory cells, and where the first die includes decoders for the array.Type: ApplicationFiled: June 20, 2020Publication date: October 8, 2020Applicant: Monolithic 3D Inc.Inventor: Zvi Or-Bach
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Patent number: 10777540Abstract: A 3D semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, and where the second die has a thickness of less than four microns.Type: GrantFiled: June 24, 2019Date of Patent: September 15, 2020Assignee: Monolithic 3D Inc.Inventor: Zvi Or-Bach
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Publication number: 20200259048Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including at least one LED driving circuit; a second single crystal layer including a first plurality of light emitting diodes (LEDs), where the second single crystal layer is on top of the first single crystal layer, where the second single crystal layer includes at least ten individual first LED pixels; and a second plurality of light emitting diodes (LEDs), where the 3D micro display includes an oxide to oxide bonding structure.Type: ApplicationFiled: April 27, 2020Publication date: August 13, 2020Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar
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Publication number: 20200243423Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, where the first level is overlaid by a first isolation layer; a second level including second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, and where the first isolation layer and the second isolation layer are separated by a distance of less than four microns.Type: ApplicationFiled: April 19, 2020Publication date: July 30, 2020Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Publication number: 20200243487Abstract: A 3D semiconductor device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a trap-rich layer disposed between the first level and the second level; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the plurality of connection paths includes vertical connections connecting from the first interconnections to the second interconnections, where the third layer includes crystalline silicon, and where the second level is bonded to the first level.Type: ApplicationFiled: April 11, 2020Publication date: July 30, 2020Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist
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Publication number: 20200194416Abstract: A method to process a 3D device, the method including: providing a first substrate including a first level including a first single crystal silicon layer and a plurality of first transistors; providing a second substrate including a second level including a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of the second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of the SiGe layer; forming a plurality of third transistors including the third single crystal silicon layer; forming a plurality of metal layers interconnecting the plurality of third transistors; and then performing a hybrid bonding of the second level onto the first level.Type: ApplicationFiled: February 21, 2020Publication date: June 18, 2020Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han
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Publication number: 20200185372Abstract: A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where a vertical distance from the first single crystal transistors to the second single crystal transistors is less than four microns, where the first level includes a plurality of processors, and where the second level includes a plurality of memory cells.Type: ApplicationFiled: February 10, 2020Publication date: June 11, 2020Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han
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Patent number: 10679977Abstract: A 3D micro display, the micro display including: a first single crystal layer including at least one LED driving circuit; and a second single crystal layer including a plurality of light emitting diodes (LEDs), where the second single crystal layer overlays the first single crystal layer, where the second single crystal layer includes at least ten first LED pixels, and where the second single crystal layer and the first single crystal layer are separated by a vertical distance of less than ten microns.Type: GrantFiled: March 14, 2018Date of Patent: June 9, 2020Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar
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Publication number: 20200176420Abstract: A 3D semiconductor device, the device including: a first level; a second level; and a third level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed directly above the first level and includes a first plurality of arrays of memory cells, where the third level is disposed directly above the second level and includes a plurality of RF circuits, and where a portion of interconnections between the plurality of logic circuits includes the RF circuits.Type: ApplicationFiled: September 2, 2019Publication date: June 4, 2020Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
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Patent number: 10658358Abstract: A 3D semiconductor wafer, the wafer including: a first device, where the first device includes a first level, the first level including first transistors, and where the first device includes a second level, the second level including first interconnections; a second device overlaying the first device, where the second device includes a third level, the third level including second transistors, and where the second device includes a fourth level, the fourth level including second interconnections, where the first device is substantially larger in area than the second device; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors.Type: GrantFiled: January 21, 2019Date of Patent: May 19, 2020Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist
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Publication number: 20200083196Abstract: A method to form a 3D semiconductor device, the method including: providing a first wafer including first circuits including transistors and interconnection; preparing a second wafer including a silicon layer; performing growth of an epitaxial layer on top of the silicon layer, the epitaxial layer including non-silicon atoms, forming second circuits over the second wafer, the second circuits including transistors and interconnection; transferring and then bonding the second wafer on top of the first wafer; and then thinning the second wafer to a thickness of less than ten microns.Type: ApplicationFiled: November 13, 2019Publication date: March 12, 2020Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist
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Publication number: 20200013800Abstract: A 3D memory device, the device including: a first horizontal bit-line; a second horizontal bit-line disposed above the first horizontal bit-line, where the first horizontal bit-line and the second horizontal bit-line function as a source or a drain for a plurality of parallel vertically-oriented memory transistors, where the first horizontal bit-line and the second horizontal bit-line are self-aligned being formed following the same lithography step; and conductive memory control lines, where a first portion of the conductive memory control lines are disposed at least partially directly underneath the plurality of parallel vertically-oriented memory transistors, and where a second portion of the conductive memory control lines are disposed at least partially directly above the plurality of parallel vertically-oriented memory transistors.Type: ApplicationFiled: July 30, 2019Publication date: January 9, 2020Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han
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Publication number: 20200013791Abstract: A 3D memory device, the device including: a first vertical pillar; a second vertical pillar, where the first vertical pillar and the second vertical pillar function as a source or a drain for a plurality of overlaying horizontally-oriented memory transistors, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following the same lithography step; and memory control circuits, where the memory control circuits are disposed at least partially directly underneath the plurality of overlaying horizontally-oriented memory transistors, or are disposed at least partially directly above the plurality of overlaying horizontally-oriented memory transistors.Type: ApplicationFiled: February 3, 2018Publication date: January 9, 2020Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han, Eli Lusky
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Publication number: 20190363179Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, where the first level is overlaid by a first isolation layer; a second level including single crystal second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, and where the first isolation layer and the second isolation layer are separated by a distance of less than four microns.Type: ApplicationFiled: August 9, 2019Publication date: November 28, 2019Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Publication number: 20190363001Abstract: A 3D semiconductor memory, the memory including: a first level including first memory cells, first transistors, and a first control line, where the first memory cells each include one of the first transistors; a second level including second memory cells, second transistors, and a second control line, where the second memory cells each include one of the second transistors, where the second level overlays the first level, where the second control line and the first control line have been processed following the same lithography step and accordingly are self-aligned, where the first control line is directly connected to each source or drain of at least five of the first transistors, and where the second control line is directly connected to each source or drain of at least five of the second transistors; and an oxide layer disposed between the first control line and the second control line.Type: ApplicationFiled: August 10, 2019Publication date: November 28, 2019Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar, Zeev Wurman, Israel Beinglass
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Publication number: 20190312014Abstract: A 3D semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, and where the second die has a thickness of less than four microns.Type: ApplicationFiled: June 24, 2019Publication date: October 10, 2019Applicant: Monolithic 3D Inc.Inventor: Zvi Or-Bach
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Patent number: 10418369Abstract: A multilevel semiconductor device including: a first level including a first array of first memory cells and first control line; a second level including a second array of second memory cells and second control line; a third level including a third array of third memory cells and third control line, where the second level overlays the first, and where the third level overlays the second; a first, second and third access pillar; memory control circuits designed to individually control cells of the first, second and third memory cells, where the device includes an array of units, where each of the units includes a plurality of the first, second and third memory cells, and a portion of the memory control circuits, where the array of units include at least eight rows and eight columns of units, and where the memory control is designed to control independently each of the units.Type: GrantFiled: May 26, 2018Date of Patent: September 17, 2019Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han
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Publication number: 20190273121Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer; first transistors overlaying the first single crystal layer; second transistors overlaying the first transistors; and a second level including a second single crystal layer, the second level overlays the second transistors, where the first transistors and the second transistors each includes a polysilicon channel.Type: ApplicationFiled: May 11, 2019Publication date: September 5, 2019Applicant: Monolithic 3D Inc.Inventors: Deepak C. Sekar, Zvi Or-Bach
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Publication number: 20190273069Abstract: A 3D semiconductor device, the device including: a first single crystal layer; at least one first metal layer above the first single crystal layer; a second metal layer above the first metal layer; a plurality of first transistors atop the second metal layer; a plurality of second transistors atop the second transistors; a plurality of third transistors atop the second transistors; a third metal layer above the plurality of third transistors: a fourth metal layer above the third metal layer; and a second single crystal layer above the fourth metal layer; and a plurality of connecting metal paths from the fourth metal layer to the second metal layer, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error, where the fourth metal layer is providing global power distribution to the device.Type: ApplicationFiled: May 12, 2019Publication date: September 5, 2019Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist