Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors overlaying the at least one first metal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell overlaying the memory peripheral circuits; and a second memory cell overlaying the first memory cell, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type.

Abstract: A semiconductor device, the device including: a plurality of memory cells; and peripheral circuits, the peripheral circuits include controlling the plurality of memory cells, where each of the plurality of memory cells includes a first gate and a second gate, where the plurality of memory cells each include a channel region, at least one channel facet, a charge trap region and a tunneling region, where a portion of the peripheral circuits are designed to control the first gate and the second gate so to position two distinct memory sites, a first memory site and second a memory site, within the charge trap region of the at least one channel facet of at least one of the plurality of memory cells, and where the first memory site is substantially closer to the first gate than the second memory site.

Abstract: A 3D device, the device including: a first stratum of first bit-cell memory arrays; a second stratum of second bit-cell memory arrays; and a third stratum, where the second stratum overlays the first stratum, where the third stratum overlays the second stratum, where the third stratum includes a plurality of word-line decoders to control the first bit-cell memory arrays and the second bit-cell memory arrays.

Abstract: A 3D semiconductor device including: a first die, comprising a first die area and a plurality of first die top contacts; a second die, comprising a second die area and a plurality of first bottom contacts; and a third die, comprising a third die area and a plurality of second bottom contacts, wherein said first die area is greater than the sum of said second die area and said third die area, wherein said second die and said third die are both placed on top of said first die laterally with respect to each other, wherein said plurality of first bottom contacts are connected to said first die top contacts, and wherein said plurality of second bottom contacts are connected to said first die top contacts.

Abstract: A semiconductor device including: a first layer including a first memory cell, the first memory cell including a first transistor; a second layer including a second memory cell, the second memory cell including a second transistor; a periphery layer including a memory peripherals transistor, the periphery layer is disposed underneath the first layer; a memory including at least the first memory cell and the second memory cell, where the second memory cell overlays the first memory cell, where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where a peripherals circuit includes the memory peripherals transistor and controls the memory; a first external connections underlying the periphery layer, the first external connections includes connections from the device to a first external device; and a second external connections overlying the second layer, the second external connections includes connections from the dev

Abstract: A 3D semiconductor wafer, the wafer including: a first device, where the first device includes a first level, the first level including first transistors, and where the first device includes a second level, the second level including first interconnections; a second device overlaying the first device, where the second device includes a third level, the third level including second transistors, and where the second device includes a fourth level, the fourth level including second interconnections, where the first device is substantially larger in area than the second device; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors.

Abstract: A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells includes one first transistor, where each of the second memory cells includes one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having the same doping type, and where the forming at least one third level includes forming a window within the third level so to allow a lithography alignment through the third level to an alignment mark disposed und

Abstract: A multilevel semiconductor device, including: a first level including a first array of first memory cells, each cell includes one first transistor; a second level including a second array of second memory cells, each cell includes one second transistor; a third level including a third array of third memory cells, each cell includes one third transistor, where second level overlays first level and third level overlays second level; memory control circuits connected so to individually control cells of the first, second and third memory cells, an array of units, each unit includes a plurality of the first, second and third memory cells and a portion of the memory control circuits, the array of units includes at least four rows and four columns of units, at least one of the first transistor is self-aligned to at least one of the third transistor, being formed following the same lithography step.

Abstract: A method for producing a 3D memory device including: providing a first level including a single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; performing additional processing steps to form memory cells within the second level and within the third level, each of the first memory cells include one first transistor, each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having the same doping type, the memory is NAND, the first level includes memory peripheral circuits, at least one of the first memory cells is at least partially atop a portion of the peripheral circuits.

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors; contact plugs; a first metal layer, where the contact plugs are connected to the plurality of first single crystal transistors and the first metal layer, where the first metal layer interconnect the first single crystal transistors forming memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a second metal layer; a third metal layer, where the second metal layer overlays the third level, where the third metal layer overlays the second metal layer, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, where the memory control circuits include control sub-circuits to remap a degraded memory block to an alternative memory space within th

Abstract: A 3D semiconductor device including: a first level including a single crystal layer, a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the single crystal layer and includes interconnects between the first transistors forming control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; and polysilicon pillars, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the third transistors, where at least one of the second memory cells is at least partially atop of the control circuits.

Abstract: A 3D semiconductor device including: a first level comprising first single crystal transistors, a first metal layer, and a plurality of latches; a second level comprising a plurality of second transistors, wherein said second level comprises first memory cells, and wherein said first memory cells each comprise at least one of said plurality of second transistors; a third level comprising a plurality of third transistors, wherein said third level comprises second memory cells, wherein said second memory cells each comprise at least one of said plurality of third transistors, wherein said second level overlays said first level, and wherein said third level overlays said second level; a second metal layer overlaying said third level, said second metal layer comprising a plurality of bit-lines, wherein said plurality of second transistors are aligned to said first single crystal transistors with less than 100 nm alignment error, wherein said plurality of second transistors are junction-less transistors, and where

Abstract: A 3D semiconductor device, the device including: a first layer including first transistors each including a first silicon channel; a second layer including second transistors each including a second silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer overlying the second transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistors are junction-less transistors.

Abstract: A 3D semiconductor device including: a first level including first single crystal transistors and a first metal layer; a second level including a plurality of second transistors; where the second level includes memory cells including the plurality of second transistors; a third level including a plurality of third transistors, where the second level overlays the first level, and where the third level overlays the second level; a second metal layer overlaying the third level; and vertically oriented conductive plugs, the vertically oriented conductive plugs connect from the second transistors to the first metal layer, where the second transistors are aligned to the first transistors with less than 100 nm alignment error, where the second transistors are junction-less transistors, and where one end of at least one of the vertically oriented conductive plugs functions also as a contact to a portion of each of the plurality of second transistors.

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors; contact plugs; a first metal layer, where a portion of the contact plugs provide connections from the plurality of first single crystal transistors to the first metal layer, and where connections include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level overlays the first level, the third level overlays the second level; a second metal layer overlaying the third level; and a third metal layer overlaying the second metal layer, where second transistors are aligned to first transistors with less than 40 nm alignment error, where the second level includes first memory cells, where the third level includes second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters.

Abstract: A 3D semiconductor device including: a first level with first single crystal transistors; contact plugs; a first metal layer, where a portion of the contact plugs provide connections from the first transistors to the first metal, where connections formed logic circuits; a second level with second transistors; a third level with third transistors, where the second level overlays the first level, and where the third level overlays the second level; a second metal layer overlaying the third level, second level includes first memory cells where each of the memory cells include at least one of the second transistors; and vertically oriented conductive plugs, where the second transistors are aligned to the first transistors with less than 100 nm alignment error, where the second transistors are junction-less transistors, where one end of each of the vertically oriented conductive plugs are connected to the second metal layer, where at least one of the vertically oriented conductive plugs is disposed directly on one

Abstract: A semiconductor device, the device including: a first level of logic circuits, the logic circuits include a plurality of first transistors interconnected by a plurality of metal layers; a thermal isolation layer overlaying the first level; a second level of memory circuits, the memory circuits include an array of memory cells, where the second level is overlaying the thermal isolation layer; and connections from the logic circuits to the memory array including vias, where the vias have a diameter of less than 400 nm, and where a majority of the thermal isolation layer includes a material with a less than 0.5 W/m·K thermal conductivity.

Abstract: A 3D semiconductor device, the device including: a first layer including a first single crystal transistor; a second layer including second transistors; a third layer including third transistors; a fourth layer including fourth transistors, where the first layer is overlaid by the second layer, where the second layer is overlaid by the third layer, and where the third layer is overlaid by the fourth layer; where a plurality of the fourth transistors are aligned to the plurality of the first single crystal transistor with less than 40 nm alignment error, where the third transistors are junction-less transistors (JLT), where each of the fourth transistors include a transistor channel, a drain and a source, and where the transistor channel is significantly narrower than the drain or the source.

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a logic strata including logic and a memory strata including memory; then performing a first placement of the logic strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; where the 3D Integrated Circuit includes through silicon vias for connection between the logic strata and the memory strata; and performing a second placement of the memory strata based on the first placement, where the logic includes at least one decoder representation for the memory, where the at least one decoder representation has a virtual size with width of contacts for the through silicon vias, and where the performing a first placement includes using the decoder representation instead of an actual memory decoder.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.