Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the plurality of logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Serializer/Deserializer (“SerDes”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.

Abstract: A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a plurality of fourth transistors overlaying, at least in part the third transistors; a second metal layer overlaying, at least in part the fourth transistors; where the fourth transistors are aligned with less than 100 nm misalignment to the first transistors, where at least one of the plurality of vias has a radius of less than 200 nm, where a memory cell includes at least one of the third transistors.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors underlying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell underlying the memory peripheral circuits; a second memory cell underlying the first memory cell, and a non-volatile NAND memory, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type, here the non-volatile NAND memory includes the first memory cell, and where at least one of the second transistors includes a polysilicon channel.

Abstract: A 3D semiconductor device, the device including: a first layer including first transistors each including a silicon channel; a second layer including second transistors each including a silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer underlying the first transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistor is a junction-less transistor.

Abstract: A multilevel semiconductor device including: a first level including a first array of first memory cells and first control line; a second level including a second array of second memory cells and second control line; a third level including a third array of third memory cells and third control line, where the second level overlays the first, and where the third level overlays the second; a first, second and third access pillar; memory control circuits designed to individually control cells of the first, second and third memory cells, where the device includes an array of units, where each of the units includes a plurality of the first, second and third memory cells, and a portion of the memory control circuits, where the array of units include at least eight rows and eight columns of units, and where the memory control is designed to control independently each of the units.

Abstract: A 3D semiconductor, the device including: a first level including a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a plurality of second transistors overlaying the first metal layer, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where the plurality of second transistors are vertically oriented transistors, and where the plurality of second transistors are at least partially directly overlaying the NAND logic structure; a memory cell; and a second metal layer overlaying the plurality of second transistors, where the second metal layer is aligned to the first metal layer with less than 40 nm misalignment, where the second transistors include a p type source and a p type drain.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors and forming a plurality of logic gates; a first intermediate metal layer overlaying the at least one metal layer; a second intermediate metal layer overlaying the first intermediate metal layer; where the first intermediate metal layer has a first current carrying capacity, where the second intermediate metal layer has a second current carrying capacity, and where the first current carrying capacity is significantly greater than the second current carrying capacity; a plurality of second transistors overlaying the second intermediate metal layer; and a top metal layer overlaying the second transistors; and a memory cell, where at least one of the second transistors includes a polysilicon transistor channel, where the second transistors are precisely aligned to the first transistors.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and at least one metal layer, where the at least one metal layer interconnecting the first transistors; a plurality of logic gates including the at least one metal layer interconnecting the first transistors; a plurality of second transistors overlaying the at least one metal layer; a plurality of third transistors overlaying the second transistors; a top metal layer overlaying the third transistors; and a memory array including wordlines, where the memory array includes at least four rows by four columns of memory mini arrays, where each of the mini arrays includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second transistors or at least one of the third transistors.

Abstract: A 3D semiconductor device, the device including: a substrate including a single crystal layer; a plurality of first transistors in and on the single crystal layer; at least one metal layer, where the at least one metal layer overlays the plurality of first transistors and the at least one metal layer includes connections between the first transistors, and where a portion of the connections between the first transistors form memory peripheral circuits; a stack of at least sixteen layers, where the stack of sixteen layers includes odd numbered layers and even numbered layers of a different composition and overlays the at least one metal layer, a multilevel memory structure, where the multilevel memory structure includes the stack of at least sixteen layers, where the stack of at least sixteen layers includes at least eight layers of memory cells controlled by the memory peripheral circuits.

Abstract: A 3D semiconductor device, the device comprising: a first single crystal layer comprising a plurality of first transistors; at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates; a plurality of second transistors overlaying said first single crystal layer; a plurality of third transistors overlaying said plurality of second transistors; a top metal layer overlying said third transistors; first circuits underlying said first single crystal layer; second circuits overlying said top metal layer; a first set of connections underlying said at least one metal layer, wherein said first set of connections connects said first transistors to said first circuits; a second set of connections overlying said top metal layer, wherein said second set of connections connects said first transistors to said second circuits, and wherein said first set of connections comprises a through silicon via (TSV).

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; a plurality of third transistors overlaying the second transistors; a second metal layer overlaying the third transistors; and Input/Output pads to provide connection to external devices, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Electrostatic Discharge (“ESD”) structure connected to at least one of the Input/Output pads, where at least one of the third transistors is a junction-less transistor, and where a memory cell includes at least one of the third transistors.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors overlaying the at least one first metal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell overlaying the memory peripheral circuits; and a second memory cell overlaying the first memory cell, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type.

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors, contacts, and a first metal layer, where a portion of the first single crystal transistors are interconnected, where the interconnected includes the first metal layer and the contacts, and where the portion of the first single crystal transistors are interconnected forms memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a fourth level overlaying the third level, the fourth level including a plurality of fourth transistors; and a second metal layer overlaying the fourth level, where the plurality of second transistors are aligned to the plurality of first transistors with a less than 40 nm alignment error.

Abstract: A method for processing a 3D semiconductor device, the method including: providing a wafer including a plurality of first dies, the plurality of first dies including a first transistor layer and a first interconnection layer; completing a step of transferring a plurality of second dies each overlaying at least one of the first dies, where each of the plurality of second dies includes a second transistor layer, where at least one of the plurality of first dies is substantially larger in area than at least one of the plurality of second dies, and where each of the plurality of second dies has a thickness greater than six microns; and completing a step of thinning the plurality of second dies, where each of the plurality of second dies has a thickness of less than 2 microns.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a plurality of third transistors overlaying the second transistors; a third metal layer overlaying the plurality of third transistors; and a connective metal path between the third metal layer and at least one of the first transistors, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error, where the first metal layer is powered by a first voltage and the second metal layer is powered by a second voltage.

Abstract: A multilevel semiconductor device, the device including: a first level including a first array of first programmable cells and a first control line; a second level including a second array of second programmable cells and a second control line; and a third level including a third array of third programmable cells and a third control line, where the second level overlays the first level, where the third level overlays the second level, where the first programmable cells are self-aligned to the second programmable cells, and where a programmable logic cell includes a plurality of the first programmable cells and a plurality of the second programmable cells.

Abstract: A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of non-volatile memory cells includes source diffusion lines and drain diffusion lines, at least one of the source diffusion lines and drain diffusion lines are shared by the first memory cell and the second memory cell, where the first memory cell includes a thin tunneling oxide of less than 1 nm thickness, and where the second memory cell includes a thick tunneling oxide of greater than 2 nm thickness.

Abstract: A 3D memory device, the device including: a first single crystal layer including memory peripheral circuits; a first memory layer including a first junction-less transistor; a second memory layer including a second junction-less transistor; and a third memory layer including a third junction-less transistor, where the first memory layer overlays the first single crystal layer, where the second memory layer overlays the first memory layer, where the third memory layer overlays the second memory layer, where the first junction-less transistor, the second junction-less transistor and the third junction-less transistor are formed by a single lithography and etch process, and where the first memory layer includes a nonvolatile NAND type memory.

Abstract: A 3D micro display, the micro display including: a first single crystal layer including at least one LED driving circuit; and a second single crystal layer including a plurality of light emitting diodes (LEDs), where the second single crystal layer overlays the first single crystal layer, where the second single crystal layer includes at least ten first LED pixels, and where the second single crystal layer and the first single crystal layer are separated by a vertical distance of less than ten microns.