Patents Assigned to Monolithic 3D Inc.
  • SEMICONDUCTOR SYSTEM, DEVICE AND STRUCTURE
    Publication number: 20170200715
    Abstract: An Integrated Circuit device, including: first transistors and second transistors, where the first transistors and the second transistors each include a single crystal channel, where at least one of the second transistors overlays at least one of the first transistors with less than 1 micron distance apart, and where at least one of the second transistors is a dopant segregated schottky barrier transistor.
    Type: Application
    Filed: March 27, 2017
    Publication date: July 13, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • 3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE
    Publication number: 20170186770
    Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor, the memory peripherals transistor is overlaying the second transistor or is underneath the first transistor, where the second memory cell overlays the first memory cell at a distance of less than 200 nm, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.
    Type: Application
    Filed: March 16, 2017
    Publication date: June 29, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar, Zeev Wurman, Israel Beinglass
  • Semiconductor devices and structures
    Patent number: 9691869
    Abstract: An Integrated Circuit device, including: a first layer including first transistors; and a second layer including second transistors overlaying the first layer, where the first transistors are facing down and the second transistors are facing up, and where the second layer includes a through layer via of less than 300 nm diameter.
    Type: Grant
    Filed: October 11, 2015
    Date of Patent: June 27, 2017
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • 3D MEMORY DEVICE AND STRUCTURE
    Publication number: 20170179155
    Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.
    Type: Application
    Filed: March 7, 2017
    Publication date: June 22, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • 3D SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20170162585
    Abstract: A 3D semiconductor device including: a first layer including a first monocrystalline layer, the first layer including first logic cells; a second layer including a monocrystalline semiconductor layer, the second layer overlying the first layer, the second layer including second transistors, where the logic cells include a Look-Up-Table logic cell, and where the second transistors are aligned to the first logic cells with less than 200 nm alignment error.
    Type: Application
    Filed: July 28, 2016
    Publication date: June 8, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • NOVEL SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE
    Publication number: 20170133395
    Abstract: A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of non-volatile memory cells includes source diffusion lines and drain diffusion lines, at least one of the source diffusion lines and drain diffusion lines are shared by the first memory cell and the second memory cell, where the first memory cell includes a thin tunneling oxide of less than 1 nm thickness, and where the second memory cell includes a thick tunneling oxide of greater than 2 nm thickness.
    Type: Application
    Filed: November 6, 2016
    Publication date: May 11, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE
    Publication number: 20170133432
    Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor overlaying the second transistor or underneath the first transistor, where the second memory cell overlays the first memory cell, and where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.
    Type: Application
    Filed: January 19, 2017
    Publication date: May 11, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Zeev Wurman
  • SEMICONDUCTOR MEMORY DEVICE, STRUCTURE AND METHODS
    Publication number: 20170117291
    Abstract: A multilevel semiconductor device, including: a first level including a first array of first memory cells; a second level including a second array of second memory cells, the first level is overlaid by the second level, where at least one of the first memory cells includes a vertically oriented first transistor, and where at least one of the second memory cells includes a vertically oriented second transistor, and where the first transistor includes a first single crystal channel, and where the second transistor includes a second single crystal channel, and where the first transistor is self-aligned to the second transistor.
    Type: Application
    Filed: October 24, 2016
    Publication date: April 27, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • 3D semiconductor device having two layers of transistors
    Patent number: 9613844
    Abstract: A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and overlying the first layer; and a second layer including second transistors, where the second layer thickness is less than 2 microns and greater than 5 nm, where the second layer is overlying the first interconnection layer, and where the second layer includes dice lines formed by an etch step.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: April 4, 2017
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar, Zeev Wurman, Israel Beinglass
  • Semiconductor system, device and structure
    Patent number: 9613887
    Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between at least a portion of the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; and at least one conductive structure constructed to provide power to a portion of the second transistors, where the provide power is controlled by at least one of the transistors.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: April 4, 2017
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • 3D SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20170092541
    Abstract: A 3D semiconductor device including: a first structure including first single crystal transistors; a second structure including second single crystal transistors, the second structure overlaying the first single crystal transistors, where at least one of the second single crystal transistors is at least partially self-aligned to at least one of the first single crystal transistors; and at least one thermal conducting path from at least one of the first single crystal transistors and second single crystal transistors to an external surface of the device.
    Type: Application
    Filed: July 2, 2016
    Publication date: March 30, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • 3DIC SYSTEM WITH MEMORY
    Publication number: 20170062600
    Abstract: A 3D IC based system, the system including: a first layer including first memory cells including first transistors, where the first transistors include first transistor channels; a second layer overlying the first layer, the second layer including second memory cells including second transistors, where the second transistors include second transistor channels, where the second layer includes vertically oriented doped regions, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the first transistor channels and at least one of the second transistor channels are directly coupled to at least one of the vertically oriented doped region.
    Type: Application
    Filed: November 14, 2016
    Publication date: March 2, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Yuniarto Widjaja
  • SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE
    Publication number: 20170053906
    Abstract: A device, including: a first structure including first memory cells, the first memory cells including first transistors; and a second structure including second memory cells, the second memory cells including second transistors, where the second transistors overlay the first transistors, and a plurality of memory cells control lines, where the first transistors are self-aligned to the second transistors, where a second transistor channel of the second transistors is aligned to a first transistor channel of the first transistors, the aligned is at an atomic level as would have been resulted from an epitaxial growth process.
    Type: Application
    Filed: August 22, 2016
    Publication date: February 23, 2017
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • 3D semiconductor device
    Patent number: 9509313
    Abstract: A semiconductor device comprising first layer comprising multiplicity of first transistors and, second layer comprising multiplicity of second transistors and, at least one function constructed by the first transistors are structure so it could be replaced by a function constructed by the second transistors.
    Type: Grant
    Filed: March 6, 2011
    Date of Patent: November 29, 2016
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20160343774
    Abstract: A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Zeev Wurman
  • Semiconductor device and structure
    Patent number: 9460991
    Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a first circuit including at least one of the first transistors, and the first circuit has a first circuit output connected to at least one of the second transistors, wherein the at least one of the second transistors is connected to a device output that is designed to be connected to external devices, and wherein the at least one of the second transistors is substantially larger than the at least one of the first transistors.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: October 4, 2016
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Semiconductor device and structure
    Patent number: 9460978
    Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a Phase-Lock-Loop (PLL) circuit, where the Phase-Lock-Loop (PLL) circuit is connected to at least one input structure, and where the least one input structure is designed to connect an input to the device from external devices.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: October 4, 2016
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20160218046
    Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the device includes a Phase Lock Loop (“PLL”) circuit, where the second clock distribution structure is connected to the Phase Lock Loop (“PLL”) circuit, and where the second transistors are aligned to the first transistors with less than 200 nm alignment error.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 28, 2016
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • SEMICONDUCTOR SYSTEM, DEVICE AND STRUCTURE
    Publication number: 20160204085
    Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between at least a portion of the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; and at least one conductive structure constructed to provide power to a portion of the second transistors, where the provide power is controlled by at least one of the transistors.
    Type: Application
    Filed: March 23, 2016
    Publication date: July 14, 2016
    Applicant: Monolithic 3D Inc.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20160141274
    Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a first wire structure constructed to provide power to a portion of the first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and a second wire structure constructed to provide power to a portion of the second transistors, where the second wire structure is isolated from the first wire structure to provide a different power voltage to the portion of the second transistors.
    Type: Application
    Filed: January 28, 2016
    Publication date: May 19, 2016
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist