Abstract: A novel converter circuit topology is disclosed. The converter circuit has a bridge circuit, a transformer, and a half-bridge current-doubler rectifier. An input end of the bridge circuit is connected to an input voltage node of the converter circuit. A reference end of the bridge circuit is connected to an output voltage node of the converter circuit. Opposing ends of a primary winding of the transformer are connected to bridge nodes of the bridge circuit. A secondary winding of the transformer serves as current-doubler inductors of the half-bridge current-doubler rectifier. A tap of the secondary winding is connected to the reference end of the bridge circuit.

Abstract: A method of fabricating a wide bandgap device includes providing a thin native substrate. An epitaxial layer is grown on a surface of the native substrate. After growing the epitaxial layer, a handle substrate is attached to the opposite surface of the native substrate by way of an interface layer. With the handle substrate providing mechanical support, wide bandgap devices are fabricated in the epitaxial layer using a low-temperature fabrication process. The handle substrate is detached from the native substrate after fabrication of the wide bandgap devices.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Abstract: A power converter includes a controller for driving a corresponding power switch in the power converter. The controller may have a current sense terminal adapted to sense/receive a current sense signal indicative of a current flowing through the corresponding power switch and a current limit terminal adapted to receive a reference current sense signal indicative of a current flowing through another power switch in the power converter. The controller may turn off the corresponding power switch once the current sense signal reaches a peak value of the reference current sense signal.

Abstract: A power module has a printed circuit board (PCB) having an output inductor substrate layer and an output capacitor substrate layer. Power converters of the power module are implemented using monolithic integrated circuit (IC) switch blocks that are mounted on a surface of the power module. Output voltages of the power converters are provided at output voltage nodes. The power converters include output inductors that are embedded within the output inductor substrate layer and output capacitors that are embedded within the output capacitor substrate layer. Embedded output inductors and capacitors are connected to corresponding output voltage nodes.

Abstract: A trans-inductor voltage regulator with fault detection has a plurality of transformers. Each transformer of the plurality of the transformers has a primary winding coupled to a switching circuit, and a secondary winding. Each secondary winding of each transformer of the plurality of transformers are coupled in series with a compensation inductor. The trans-inductor further has a controller operable to detect a) a short condition in a secondary side of each transformer of the plurality of transformers, b) a short condition between a primary side and the secondary side of each transformer of the plurality of transformers; c) an open condition in the primary side of each transformer of the plurality of transformers; and d) an open condition in the secondary side of each transformer of the plurality of transformers.

Abstract: A power module has a substrate with a bottom side and a component side. Power converters of the power module are implemented using monolithic integrated circuit (IC) switch blocks that are mounted on the component side of the substrate. The power converters include output inductors that are disposed within the substrate. An end of an output inductor is connected to a switch node of a monolithic IC switch block and another end of the output inductor is connected to an output voltage node of the power module.

Abstract: A resonant converter has a primary resonant tank circuit and a secondary resonant tank circuit. An inverter circuit converts an input DC voltage received by the resonant converter at an input voltage node to a pulsating signal that is fed to the primary resonant tank circuit to generate a resonant tank current that flows through a primary winding of a transformer. The resonant tank current induces current in a secondary winding of the transformer. The induced current is rectified by a rectifier and the rectified signal is filtered to generate an output DC voltage at an output voltage node. The secondary resonant tank circuit is disposed between the secondary winding of the transformer and the output voltage node, and a tank node of the secondary resonant tank is connected to the primary resonant tank circuit through the inverter circuit.

Abstract: This disclosure provides a control method for multi-phase switching converter having a master phase and at least one slave phase. The control method comprises: providing a pulse signal with 0.5 duty cycle by frequency-dividing a master control signal supplied to the master phase; and for each slave phase to be enabled, setting a ratio of a charge current and a discharge current based on a slave phase number under a phase-added operation, charging a first capacitor with the charge current and discharging a second capacitor with the discharge current in high logic of the pulse signal, discharging the first capacitor with the discharge current and charging the second capacitor with the charge current in logic low of the pulse signal, and generating a respective enable signal for controlling a switch in a corresponding slave phase by comparing a first capacitor voltage with a second capacitor voltage.

Abstract: A multiphase converter provides an output voltage to a load. The multiphase converter receives a load event signal from the load and turns ON at a same time the phases of the multiphase converter to increase the output voltage in response to the load event signal indicating that a load current drawn by the load from the multiphase converter is about to increase. The multiphase converter increases an impedance of low-side switches of the multiphase converter in response to the load event signal indicating that the load current is about to decrease.

Abstract: A power management integrated circuit (PMIC) chip provides power loss protection to an application device. The PMIC chip has several storage pins that each receives a set of storage capacitors that are charged using power from a power source during normal operation. An application device receives power from the power source during normal operation and receives power from an operational set of storage capacitors during power loss. A failing set of storage capacitors is disconnected from an operational set of storage capacitors and from the PMIC chip. The operational set of storage capacitors remains connected to the PMIC chip to provide power loss protection.

Abstract: An integrated circuit with a fault reporting structure. The integrated circuit has at least one power MOSFET having a plurality of MOSFET cells with each MOSFET cell having a drain metal and a source metal, and the integrated circuit has a power MOSFET area for routing the drain metals and the source metals of the plurality of MOSFET cells. The fault reporting structure has a metal net routed in the power MOSFET area or in an area above or below the power MOSFET area.

Abstract: An electric system has an input terminal to receive an input voltage, a system output terminal to provide a system voltage, and N charging units for charging N loads respectively. The electric system has an input switch coupled between the input terminal and a first terminal, a switching circuit coupled between the first terminal and the system output terminal. The switching circuit converts the a boost output voltage at the first terminal to the system voltage, or converts the system voltage to the boost output voltage. The electric system further has a voltage control module having N input terminals coupled to the N charging units respectively, the voltage control module senses N charging currents passing through the N charging units respectively, and adjusts the boost output voltage based on the N charging currents.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JFET also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Abstract: A resonant converter has a primary resonant tank circuit and a secondary resonant tank circuit. An inverter circuit converts an input DC voltage received by the resonant converter at an input voltage node to a pulsating signal that is fed to the primary resonant tank circuit to generate a resonant tank current that flows through a primary winding of a transformer. The resonant tank current induces current in a secondary winding of the transformer. The induced current is rectified by a rectifier and the rectified signal is filtered by an output capacitor to generate an output DC voltage at an output voltage node. The secondary resonant tank circuit is disposed between the input voltage node and the output voltage node to inject odd order harmonics of the operating frequency to the primary tank circuit to shape the resonant tank current.

Abstract: An integrated circuit of a buck-boost converter working in a buck mode with a buck power switching cycle, a boost mode with a boost power switching cycle or a buck-boost mode with a buck-boost power switching cycle. The integrated circuit integrates a first power switch, a second power switch, a third power switch and a fourth power switch, and an output current sensing circuit. The buck-boost power switching cycle consists of a first buck-boost phase, a second buck-boost phase and a third buck-boost phase. The output current sensing circuit samples the current flowing through the first power switch during the second buck-boost phase and the current flowing through the fourth power switch during the third buck-boost phase so as to generate the output current information.

Abstract: A hybrid DC-DC converter includes a converter circuit, a bridge circuit with a bridge path that includes a winding of a transformer, and another bridge circuit with a bridge path that includes another winding of the transformer. Current through the bridge path of the other bridge circuit flows through the converter circuit in one direction and bypasses the converter circuit in the other direction. The converter circuit can operate in buck, boost, or buck-boost mode.

Abstract: A multi-phase voltage converter has a plurality of integrated circuits (ICs), and a controller. Each IC has a power switch, a monitoring pin and a current sense pin. The power switch is controlled to convert an input voltage to an output voltage. The current sense pin is capable of providing a current sense signal representative of a current flowing through the power switch. The controller is capable of providing a clock signal via the monitoring pin, and provides a plurality of data signals via the current sense pin of the plurality of ICs. Each of the plurality of ICs is assigned an identification code based on the clock signal and one of the plurality of data signals.

Abstract: A power converter includes a switch control circuit for driving a high side switch of the power converter comprising the high side switch and a low side switch connected in series. The switch control circuit may have a first terminal for receiving a low side switch driving signal of the low side switch, a second terminal used as a reference ground terminal of the switch control circuit, and a third terminal used as an output terminal to provide a high side switch driving signal, the switch control circuit can draw power from the low side switch driving signal and may not require internal regulators that should sustain high voltage.

Abstract: A power management integrated circuit (PMIC) chip provides power loss protection to an application device. The PMIC chip has several storage pins that each receives a set of storage capacitors that are charged using power from a power source during normal operation. An application device receives power from the power source during normal operation and receives power from an operational set of storage capacitors during power loss. A failing set of storage capacitors is disconnected from an operational set of storage capacitors and from the PMIC chip. The operational set of storage capacitors remains connected to the PMIC chip to provide power loss protection.