Abstract: An LLC resonant converter includes a transformer, a switching half-bridge circuit, a resonant circuit, and a full-bridge rectifier. Both the switching half-bridge circuit and the full-bridge rectifier are on the same side of the transformer. The switching half-bridge circuit has a pair of switches, with one of the switches being connected to the output voltage node of the converter.

Abstract: A trans-inductor voltage regulator (TLVR) has regulator blocks and transformers. Secondary windings of the transformers are connected in series with a compensation inductor to form a trans-inductor loop, which is connected to the output voltage of the TLVR instead of to ground. Primary windings of the transformers serve as output inductors of the regulator blocks. The inductance of each output inductor and the output inductance of the TLVR are input to an averaging network of an averaging inductor direct current resistance (DCR) current sense circuit to generate an average sensed voltage. The average sensed voltage is converted to an average sensed current, which is used by a controller to generate control signals that drive the regulator blocks to generate the output voltage of the TLVR.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Abstract: A power converter includes a controller for driving a power switch in one phase of a plurality of phases of the power converter. The controller may have a first terminal for receiving an input switch driving signal which is used to drive a power switch in another phase of the power converter, and a second terminal for providing an output switch driving signal to drive the power switch in the one phase. The controller draws power from the input switch driving signal received at the first terminal, and is configured to provide the output switch driving signal based on the input switch driving signal.

Abstract: A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed four terminal JFET includes an integrated high voltage capacitor (HVC). The JFET includes a first terminal coupled to a drain region, a second terminal coupled to the source region, a third terminal coupled to the base region, and an integrated HVC terminal coupled to an integrated HVC electrode which forms an HVC with the drain region. The JFET also includes a channel formed by a channel region. A bias on the base region fully depletes the channel of majority carriers. The channel has an unbiased concentration of majority carriers. The integrated HVC electrode is positioned relative to the channel region such that applying the bias to the integrated HVC terminal depletes the channel by at most ten percent of the unbiased concentration of majority carriers.

Abstract: A MOSFET fabricated in a semiconductor substrate, includes: a gate oxide region formed atop the semiconductor substrate; a gate polysilicon region formed on the gate oxide region; a source region of a first doping type formed in the semiconductor substrate and located at a first side of the gate polysilicon region; and a drain region of the first doping type formed in the semiconductor substrate and located at a second side of the gate polysilicon region. The gate polysilicon region has a first sub-region of the first doping type, a second sub-region of the first doping type, and a third sub-region of a second doping type, wherein the first sub-region is laterally adjacent to the source region, the second sub-region is laterally adjacent to the drain region, and the third sub-region is formed laterally between the first and second sub-regions.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed four terminal JFET includes an integrated high voltage capacitor (HVC). The JFET includes a first terminal coupled to a drain region, a second terminal coupled to the source region, a third terminal coupled to the base region, and an integrated HVC terminal coupled to an integrated HVC electrode which forms an HVC with the drain region. The JFET also includes a channel formed by a channel region. A bias on the base region fully depletes the channel of majority carriers. The channel has an unbiased concentration of majority carriers. The integrated HVC electrode is positioned relative to the channel region such that applying the bias to the integrated HVC terminal depletes the channel by at most ten percent of the unbiased concentration of majority carriers.

Abstract: A method of fabricating a wide bandgap device includes providing a thin native substrate. An epitaxial layer is grown on a surface of the native substrate. After growing the epitaxial layer, a handle substrate is attached to the opposite surface of the native substrate by way of an interface layer. With the handle substrate providing mechanical support, wide bandgap devices are fabricated in the epitaxial layer using a low-temperature fabrication process. The handle substrate is detached from the native substrate after fabrication of the wide bandgap devices.

Abstract: A trans-inductor voltage regulator (TLVR) circuit has multiple phases and a regulator block for each phase. Each regulator block is connected to an output capacitor of the TLVR circuit by way of a first winding of a corresponding nonlinear transformer. A second winding of the nonlinear transformers are connected in series with a compensation inductor. The first winding of the corresponding nonlinear transformer has a first inductance when a load current is at a first level, and the first winding of the corresponding nonlinear transformer has a second inductance that is less than the first inductance when the load current is at a second level that is higher than the first level.

Abstract: An LED driving system for synchronizing two LED driving integrated circuits to drive LED strings. The LED driving system sequentially activates the LED strings driven by the first LED driving integrated circuit and then outputs a downstream enabling signal from the first LED driving integrated circuit to the second LED driving integrated circuit to activate the LED strings driven by the second LED driving integrated circuit.

Abstract: A trans-inductor voltage regulator (TLVR) circuit has multiple phases and a regulator block for each phase. Each regulator block has a winding of a transformer as an output inductor. The other windings of the transformers are connected in series with a nonlinear compensation inductor. The compensation inductor has a large inductance when the compensation inductor current is responsive to a steady state load current and has a small inductance when the compensation inductor current is responsive to a transient load current.

Abstract: A hybrid DC-DC converter includes a converter circuit, a bridge circuit with a bridge path that includes a winding of a transformer, and another bridge circuit with a bridge path that includes another winding of the transformer. Current through the bridge path of the other bridge circuit flows through the converter circuit in one direction and bypasses the converter circuit in the other direction. The converter circuit can operate in buck, boost, or buck-boost mode.

Abstract: A current sensing circuit for sensing a current flowing through a current sense resistor, wherein the current sense resistor is configured to receive a variable power input voltage. The current sensing circuit includes: a current sense amplifier having a first input terminal configured to be coupled to a first terminal of the current sense resistor to receive the power input voltage, a second input terminal configured to be coupled to a second terminal of the current sense resistor, and an output terminal for providing a current sensing signal indicative of the current flowing through the current sense resistor; and a calibration circuit configured to be coupled to the first input terminal of the current sense amplifier. The calibration circuit is configured to convert the power input voltage into a calibration current, and provide the calibration current to the current sense amplifier, so as to reduce a change in the current sensing signal caused by a change in the power input voltage.

Abstract: An inductor has one or more wires and a multipart magnetic core. The multipart magnetic core has magnetic core parts that are adjacent and magnetically coupled. The inductor provides an inductance of at least 40 nH for currents greater than 1 A and less than 60 A, and at least 20 nH for currents of at least 60 A.

Abstract: An energy recycle circuit for a flyback circuit, the flyback circuit has a primary winding of a transformer a primary switch. The energy recycle circuit has an energy recycle branch coupled in parallel with the primary winding, and an integrated circuit having a plurality of pins. The energy recycle branch has an auxiliary switch and a clamp capacitor connected in series. Among the plurality of pins, a first pin receives an external supply voltage. A second pin is used as a power ground that is different from a primary power ground. A third pin is used to sense a branch current flowing through the energy recycle branch. A fourth pin is used to control an operation of the auxiliary switch. A fifth pin that is connected to an external resistor for setting a maximum ON-time threshold of the auxiliary switch.

Abstract: A trans-inductor voltage regulator (TLVR) circuit has multiple phases and a regulator block for each phase. Each regulator block has a winding of a transformer as an output inductor. The other windings of the transformers are connected in series with a nonlinear compensation inductor. The compensation inductor has a large inductance when the compensation inductor current is responsive to a steady state load current and has a small inductance when the compensation inductor current is responsive to a transient load current.

Abstract: A power supply having at least one PMIC provides flexible control to the power manage systems. The PMIC has an enable pin configured to receive a control signal, and a clock pin configured to generate and/or receive a series of clock pulses, so as to facilitate the operation of the PMIC.

Abstract: Voltage regulators generate voltage rails that power a central processing unit (CPU). The CPU communicates power management instructions to a power supply controller that drives the voltage regulators. The power supply controller sets a voltage level of a voltage rail generated by a voltage regulator in accordance with a power management instruction received from the CPU. The power supply controller enables the voltage regulator to operate in discontinuous conduction mode (DCM) independent of power state commands from the CPU.

Abstract: A multi-input single output power system for outputting an output voltage on an output node. It includes a first integrated circuit (IC) converter device and a second IC converter device. The first IC converter device has a first pin to receive a first input voltage, a second pin to output the output voltage, and a first power unit coupled between the first pin and the second pin. The second IC converter device has a first pin to receive a second input voltage, a second pin to output the output voltage, a second power unit coupled between the first pin of the second IC converter device and the second pin of the second IC converter device, and a third pin. The third pin receives an external phase shedding control signal to determine whether to stop the second power unit from providing power to the output node.