Abstract: A power switch device driver with energy recovery is discussed. The power switch device adopts four switches and one inductor with appropriate control to insure the switching speed and save the power loss.

Abstract: A power module has a substrate with a bottom side and a component side. Power converters of the power module are implemented using monolithic integrated circuit (IC) switch blocks that are mounted on the component side of the substrate. The power converters include output inductors that are disposed within the substrate. An end of an output inductor is connected to a switch node of a monolithic IC switch block and another end of the output inductor is connected to an output voltage node of the power module.

Abstract: A LED driving system for driving a LED matrix. The LED driving system includes an interconnection structure having a first surface and a second surface opposite to the first surface and a plurality of driver dies/chips attached to the first surface of the interconnection structure. The LED matrix is divided into a plurality of sub LED matrix sections that are attached to the second surface of the interconnection structure. The interconnection structure is configured to electrically couple each one of the plurality of sub LED matrix sections to a corresponding one driver die/chip in the plurality of driver dies/chips.

Abstract: A gate driver is configured to drive a normally-on device and a normally-off device coupled in series. The gate driver controls the normally-on device in response to a PWM signal, and to control a normally-off device to maintain ON in normal operations. If an under voltage condition of a negative power supply of a first driver used to drive the normally-on device, or a positive power supply of a second driver used to drive the normally-off device, or an input supply voltage is detected, the normally-off device is controlled to be OFF.

Abstract: An LLC resonant converter including a transformer, a switching full-bridge circuit, a resonant circuit, and a bridge rectifier. The switching full-bridge circuit has a first pair of switches and a second pair of switches, with the first pair of switches being connected between a DC input voltage and a second end of a secondary winding of the transformer, the second pair of switches being connected between a DC input voltage and a first end of the secondary winding of the transformer.

Abstract: A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

Abstract: The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

Abstract: An inductor has one or more wires and a multipart magnetic core. The multipart magnetic core has magnetic core parts that are adjacent and magnetically coupled. The inductor provides an inductance of at least 40 nH for currents greater than 1 A and less than 60 A, and at least 20 nH for currents of at least 60 A.

Abstract: A 3-D package structure for isolated power module is discussed. The package structure has metal trace in a support layer (e.g. a substrate board), which is covered by two magnetic films from both sides, thus an effective transformer is formed. An IC die which contains a voltage regulator is stacked above the support layer, which significantly reduces the package size.

Abstract: A trans-inductor voltage regulator (TLVR) has regulator blocks and transformers. Secondary windings of the transformers are connected in series with a compensation inductor to form a trans-inductor loop, which is connected to the output voltage of the TLVR instead of to ground. Primary windings of the transformers serve as output inductors of the regulator blocks. The inductance of each output inductor and the output inductance of the TLVR are input to an averaging network of an averaging inductor direct current resistance (DCR) current sense circuit to generate an average sensed voltage. The average sensed voltage is converted to an average sensed current, which is used by a controller to generate control signals that drive the regulator blocks to generate the output voltage of the TLVR.

Abstract: A multi-phase voltage converter has a plurality of integrated circuits (ICs), and a controller. Each IC has a control pin to receive a control signal, a monitoring pin and a temperature sensing circuit, the controller has a monitoring pin connected to the monitoring pin of each of the plurality of ICs to receive a monitoring signal. The temperature sensing circuit is connected to or disconnected from the monitoring pin of the corresponding one of the plurality of ICs in response to the control signal and the monitoring signal.

Abstract: An LLC resonant converter includes a transformer, a switching half-bridge circuit, a resonant circuit, and a full-bridge rectifier. Both the switching half-bridge circuit and the full-bridge rectifier are on the same side of the transformer. The switching half-bridge circuit has a pair of switches, with one of the switches being connected to the output voltage node of the converter.

Abstract: A trans-inductor voltage regulator (TLVR) has regulator blocks and transformers. Secondary windings of the transformers are connected in series with a compensation inductor to form a trans-inductor loop, which is connected to the output voltage of the TLVR instead of to ground. Primary windings of the transformers serve as output inductors of the regulator blocks. The inductance of each output inductor and the output inductance of the TLVR are input to an averaging network of an averaging inductor direct current resistance (DCR) current sense circuit to generate an average sensed voltage. The average sensed voltage is converted to an average sensed current, which is used by a controller to generate control signals that drive the regulator blocks to generate the output voltage of the TLVR.

Abstract: A power converter includes a controller for driving a power switch in one phase of a plurality of phases of the power converter. The controller may have a first terminal for receiving an input switch driving signal which is used to drive a power switch in another phase of the power converter, and a second terminal for providing an output switch driving signal to drive the power switch in the one phase. The controller draws power from the input switch driving signal received at the first terminal, and is configured to provide the output switch driving signal based on the input switch driving signal.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Abstract: A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed four terminal JFET includes an integrated high voltage capacitor (HVC). The JFET includes a first terminal coupled to a drain region, a second terminal coupled to the source region, a third terminal coupled to the base region, and an integrated HVC terminal coupled to an integrated HVC electrode which forms an HVC with the drain region. The JFET also includes a channel formed by a channel region. A bias on the base region fully depletes the channel of majority carriers. The channel has an unbiased concentration of majority carriers. The integrated HVC electrode is positioned relative to the channel region such that applying the bias to the integrated HVC terminal depletes the channel by at most ten percent of the unbiased concentration of majority carriers.

Abstract: A MOSFET fabricated in a semiconductor substrate, includes: a gate oxide region formed atop the semiconductor substrate; a gate polysilicon region formed on the gate oxide region; a source region of a first doping type formed in the semiconductor substrate and located at a first side of the gate polysilicon region; and a drain region of the first doping type formed in the semiconductor substrate and located at a second side of the gate polysilicon region. The gate polysilicon region has a first sub-region of the first doping type, a second sub-region of the first doping type, and a third sub-region of a second doping type, wherein the first sub-region is laterally adjacent to the source region, the second sub-region is laterally adjacent to the drain region, and the third sub-region is formed laterally between the first and second sub-regions.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed four terminal JFET includes an integrated high voltage capacitor (HVC). The JFET includes a first terminal coupled to a drain region, a second terminal coupled to the source region, a third terminal coupled to the base region, and an integrated HVC terminal coupled to an integrated HVC electrode which forms an HVC with the drain region. The JFET also includes a channel formed by a channel region. A bias on the base region fully depletes the channel of majority carriers. The channel has an unbiased concentration of majority carriers. The integrated HVC electrode is positioned relative to the channel region such that applying the bias to the integrated HVC terminal depletes the channel by at most ten percent of the unbiased concentration of majority carriers.

Abstract: A method of fabricating a wide bandgap device includes providing a thin native substrate. An epitaxial layer is grown on a surface of the native substrate. After growing the epitaxial layer, a handle substrate is attached to the opposite surface of the native substrate by way of an interface layer. With the handle substrate providing mechanical support, wide bandgap devices are fabricated in the epitaxial layer using a low-temperature fabrication process. The handle substrate is detached from the native substrate after fabrication of the wide bandgap devices.