Abstract: To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

Abstract: Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. The plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer The patterned silicon nitride layer and the patterned pad oxide layer are removed to expose a surface of the substrate as an active area of the semiconductor device. An ion drive-in to the active area on the substrate is performed by directing a flow of oxygen and nitrogen toward the substrate at a predetermined temperature and with a sufficient amount of oxygen to at least substantially prevent silicon nitride from forming on the field oxide regions. The method further comprises forming a sacrificial oxide layer on the active area, removing the sacrificial oxide layer to expose the active area, and forming a gate oxide layer on the active area.

Abstract: Embodiments of the present invention are directed to a method of forming a bottom oxide layer in the trench in semiconductor devices, such as Double-Diffused Metal-Oxide Semiconductor (DMOS) devices. In one embodiment, a method of forming a bottom oxide layer in a trench structure comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming a first oxide layer on the silicon nitride layer; forming a trench structure in the semiconductor substrate; forming a second oxide layer on a bottom and sidewalls of the trench and on a surface of the first oxide layer; removing the first oxide layer and the second oxide layer on the surface of the silicon nitride layer; and removing the second oxide layer on the sidewalls of the trench and a portion of the second oxide layer on the bottom of the trench.

Abstract: An applying method for an adhesive according to an embodiment includes the following steps. First, gas is exhausted from a first exhaust pipe, so as to eliminate a part of the gas in a closed container. Next, the gas continues to be exhausted from the first exhaust pipe, so as to have the adhesive in the transmission pipeline become bubbled, and also to convey the bubbled adhesive to reach the supply vent. Later, gas is exhausted from the second exhaust pipe and continues to be exhausted from the first exhaust pipe, so as to greatly exhaust the gas in the closed container, and also to increase bubbling in the adhesive. Subsequently, the gas continues to be exhausted from the second exhaust pipe and ceases to be exhausted from the first exhaust pipe, so as to cause the adhesive to reach a gasified state. Also the gasified adhesive is supplied to the closed container from the supply vent, so that the gasified adhesive can adhere to and coat above the SiO2 layer.

Abstract: In one embodiment of the invention, a semiconductor device set comprises at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and comprises a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide layer. The trench-typed termination structure has a trench profile and comprises an oxide layer in the trench profile. A termination polysilicon layer with discrete features separates the termination polysilicon layer. An isolation layer covers the termination polysilicon layer and filling the discrete features. The trench-typed MOSFET and the trench-typed termination structure may be formed on a DMOS device comprising an N+ silicon substrate, an N epitaxial layer on the N+ silicon substrate, and a P epitaxial layer on the N epitaxial layer. The trench profiles of the trench-typed MOSFET and of the trench-typed termination structure may penetrate through the P epitaxial layer into the N epitaxial layer.

Abstract: A method of plasma etching a metal stack on a semiconductor wafer is presented. The metal stack includes an aluminum layer overlaid with a titanium-containing anti-reflective coating (ARC) layer. The method includes flowing a fluorine-containing species (e.g., SF6) and a chlorine-containing species (e.g., BCl3 and Cl2) into a plasma etch chamber while etching the titanium-containing ARC layer.

Abstract: A method of etching nitride over oxide is provided for the formation of vertical profile nitride spacers with high uniformity while maintaining the integrity of underlying thin oxide layers. The method includes providing a first gas flow including a first fluorocarbon and a second fluorocarbon at a first ratio, applying a first quantity of power to the first gas flow to create a first plasma, etching a first portion of a silicon nitride layer with the first plasma, providing a second gas flow including the first fluorocarbon and the second fluorocarbon at a second ratio greater than the first ratio, applying a second quantity of power to the second gas flow to create a second plasma, and etching a second portion of the silicon nitride layer with the second plasma.

Abstract: Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of row structures (280). Each row structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the row structures before the conductive layer (160) for the wordlines is deposited. The pedestals are formed in the area of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals raise the top surface of the wordline layer near the contact openings, so the contact opening etch can be made shorter. The pedestals also increase the minimum thickness of the wordline layer near the contact openings, so the loss of the wordline layer during the etch of the contact openings becomes less critical, and the photolithographic tolerances required for patterning the contact openings can be relaxed. The pedestals can be dummy structures (they may have no electrical functionality).

Abstract: An interconnect for a substructure having an opening (470) with a rounded perimetrical top edge (480) includes a titanium nitride layer (150) and a tungsten layer (160). The titanium layer overlies the substructure, extends into the opening, has a substantially columnar grain structure, and is less than 30 nm thick. The tungsten layer overlies/contacts the titanium nitride layer and extends into the opening. A titanium layer (140) normally no more than 36 nm thick is typically situated between the substructure and the titanium nitride layer.

Abstract: A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.

Abstract: Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (160) that is thin in some regions, such as the cell region, and thicker in other regions (165), such as the periphery region. The method simultaneously provides a gate oxide layer with two or more thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to a specific embodiment of the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor ROM device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor ROM device.

Abstract: A method for producing an ultraviolet light (UV) transmissive silicon nitride layer in a plasma enhanced chemical vapor deposition (PECVD) reactor is presented. The UV transmissive film is produced by reducing, in comparison to a standard silicon nitride process, a flow rate of the silane and ammonia gas precursors to the PECVD reactor, and significantly increasing a flow rate of nitrogen gas to the reactor. The process reduces the concentration of Si—H bonds in the silicon nitride film to provide UV transmissivity. Further, the amount of nitrogen in the film is greater than in a standard PECVD silicon nitride film, and as a percentage constitutes a greater part of the film than silicon. The film has excellent step coverage and a low number of pinhole defects. The film may be used as a passivation layer in a UV erasable memory integrated circuit.

Abstract: Embodiments of the present invention relate to a process for filling a trench structure of a semiconductor device to prevent formation of voids in the trench structure so as to minimize current leakage and provide excellent electrical properties. In one embodiment, a process for filling a trench of a semiconductor device comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming an oxide layer on the silicon nitride layer; partially removing the oxide layer, the silicon nitride layer and the semiconductor substrate to form at least one trench; forming a sacrificial oxide layer on sidewalls of the trench; removing the sacrificial oxide layer; performing an etching procedure to remove portions of the silicon nitride layer protruding from the sidewalls of the trench so as to form substantially even sidewalls of the trench; and forming a trench-fill layer to fill the trench and deposit on the oxide layer.

Abstract: A method for locating wiring swap in a hi-fix structure of a simultaneous multi-electronic device test system is introduced to screen the complicated wiring state of the hi-fix structure and to pinpoint the wiring swap thereinside as well. The hi-fix structure has at least S socket slots for testing electronic devices which each of the electronic devices has at least R leads. The present method, firstly, is to prepare R test unit sets which each of the test unit set includes S identical lead-off elements. Then, all R test unit sets are tested, in order, on the hi-fix structure and the respective test results are recorded. Finally, by analyzing the test results, the wiring swap inside the hi-fix structure can be accurately located.

Abstract: In a polishing process (e.g. CMP), the endpoint is declared after (a) detecting that the friction between the polishing tool and the structure being polished is rising, then (b) determining that the friction is falling, then (c) waiting for a predetermined period of time (which can be zero). This algorithm results in reduced over-polishing in some embodiments. Other embodiments are also described.

Abstract: A photoresist layer is exposed two or more times. At least one exposure is conducted through a regular mask, and at least one exposure through a modified mask with a clear region overlapping the position of a non-clear region of the first mask. The radiation dose used with the modified mask is insufficient by itself to create a resist pattern on the substrate. The exposure through the modified mask alleviates the resist underexposure in concave corners of the opaque pattern of the regular mask. Instead of the modified mask, an exposure without a mask can be performed.

Abstract: Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage.

Abstract: Embodiments of the invention are directed to a method of forming a bottom oxide in a trench structure. In one embodiment, the method includes steps of providing a semiconductor substrate and forming a trench structure in the semiconductor substrate; performing an PECVD process with TEOS as a source to deposit an oxide layer on the bottom and sidewall of the trench structure and the semiconductor substrate; and removing the oxide layer on the sidewall of the trench structure substantially completely and the oxide layer on the bottom of the trench structure partially to define the remained oxide layer as the bottom oxide layer.

Abstract: Disclosed is an apparatus and method for controlling boiling condition of hot H3PO4 solution by adjusting the vapor extracting rate thereof, wherein an acid tank filled with hot H3PO4 solution to a level surface is located in a treatment room and a temperature thermocouple is arranged above the level surface of the hot H3PO4 solution to monitor the vapor temperature near the level surface of the H3PO4 solution. The vapor temperature is used to adjust the extracting rate of the treatment room by control of a damper connected to an outlet of the treatment room. According to the present invention, the treatment apparatus and method can control the boiling condition of the hot H3PO4 solution thereof by properly adjusting the extracting rate, and therefore avoid defects and loss of control in manufacturing processes.