Abstract: A system and method for finding operation/tool's combination which causes the integration failure in a semiconductor fabrication facility is disclosed. It comprises the steps of generating a candidate operation/tool list by selecting the operation/tool's that are more likely to cause said failure. Assign a weight value to each lot in the lot list for each operatioon/tool in said candidate operation/tool list, the weight value being a predetermined positive value for a bad lot, and a negative value for a good lot. Then select any pair of operation/tool's from said candidate operation/tool list and calculate a peak combination cumulative value for that pair of operation/tool's. Rank each pair of operation/tool's according to their corresponding peak combination cumulative values. It is determined the pair of operation/tool's with the greatest peak combination cumulative value the most likely to cause said failure.

Abstract: Embodiments of the present invention relate to an apparatus for spin drying substrates in a spin dryer tank. A spin dryer cover is movable between a closed position to close an opening of the spin dryer tank and an open position to open the spin dryer tank, and a cylinder is coupled with the spin dryer cover. The cylinder is movable in a first operation to move the spin dryer cover to the open position and movable in a second operation to move the spin dryer cover to the closed position. A system for sensing the position of the spin dryer cover comprises a cylinder sensor configured to sense the first operation and the second operation of the cylinder. A cover sensor is configured to sense the position of the spin dryer cover. A logic circuit is configured to output a cover opening signal indicating that the spin dryer cover is in the open position when the cylinder sensor senses the first operation of the cylinder and the cover sensor senses that the spin dryer cover is in the open position.

Abstract: A chemical mechanical polishing apparatus has a plurality of electric machines for executing mechanical polishing motions, at least two control systems for controlling the mechanical polishing motions, at least two signal wires connected with the two control systems for transmitting signals of the two control systems, and a wave filter comprising two terminals connected with the two signal wires respectively for filtering out the signal whose voltage exceeds a predetermined value in the two signal wires.

Abstract: In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

Abstract: Embodiment of the present invention are directed to improving the performance of a DMOS transistor. A method of fabricating a DMOS transistor comprises providing a semiconductor substrate having a gate oxide and a trenched gate, and implanting first conductive dopants into a surface of the semiconductor substrate adjacent to the trenched gate to form a first doping region. An insulating layer is deposited over the semiconductor substrate; and selectively etching the insulating layer to form a source contact window over a central portion of the first doping region and to leave an insulator structure above the trenched gate. The source contact window of the insulating layer has an enlarged top portion which is larger in size than a bottom portion of the source contact window closer to the first doping region than the enlarged top portion. The enlarged top portion is typically bowl-shaped.

Abstract: In a nonvolatile memory, a floating gate (124) is covered with ONO (98), and a control gate polysilicon layer (124) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer (101) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion (98.2) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric (210) is therefore reduced. Other embodiments are also provided.

Abstract: A memory device includes a first memory cell and a second memory cell both controlled by a common control gate. The device includes: a substrate; first and second stacks each including an insulating layer formed over the substrate, a first conductive layer formed over the insulating layer and providing a select gate, and a first dielectric layer formed over the first conductive layer, each of the stacks also including an inner sidewall and an outer sidewall, the. stacks being separated by a common area of the substrate, the inner and outer sidewalls of the stacks being coated with a second dielectric layer; first and second spacers formed adjacent the inner sidewalls of the first and second stacks respectively, the first and second spacers being separated by a medial portion of the common source area of the substrate, each of the spacers.

Abstract: In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

Abstract: An integrated data input sorting and timing circuit for double data rate (“DDR”) dynamic random access memory (“DRAM”) devices in which a sorting of the input data into odd/even is integrated with the necessary timing to allow synchronization with the on-chip Y-clock signal (column address select) without the need to provide separate circuits. In those devices having multiple DQS inputs, any skew between DQS pins is allowed as long as no one DQS pin violates the DQS-to-clock (“DQS-CLK”) skew requirements. The circuit and method of the present invention also allows a write to occur at command +2 cycles (last data+½). Functionally, both rising and falling data (i.e., data on the rising and falling edges of DQS) is captured by the DQS inputs and presented in parallel to the chips internal write path and data is passed on the falling edge of DQS.

Abstract: Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

Abstract: Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer on the substrate; defining the mask oxide layer to form a patterned mask oxide layer and exposing a partial surface of the substrate to form a window; and using the patterned mask oxide layer as an etching mask to form the trench in the window. A first oxide layer is formed on the sidewall and the bottom of the trench of the substrate. A photoresist layer is formed on the substrate, filling the trench of the substrate. The method further comprises partially etching back the photoresist layer to leave a remaining photoresist layer in the trench. The height of the remaining photoresist layer is lower than the depth of the trench. A curing treatment of the remaining photoresist layer is performed after the partial etching.

Abstract: Embodiments of the present invention relate to a method of making an IC capacitor. In one embodiment, the method comprises providing a substrate, forming a polycide layer on the substrate, and forming an insulating amorphous silicon layer on the polycide layer. The insulating amorphous silicon layer serves as an anti-reflection layer. The method further comprises implanting n-type ions into the insulating amorphous silicon layer to transform the insulating amorphous silicon layer into a conductive amorphous silicon layer, and patterning the polycide layer and the conductive amorphous silicon layer to form a bottom electrode on the substrate. A dielectric layer is formed on the bottom electrode and the substrate, and a conductor layer is formed on the dielectric layer. The conductor layer is patterned to form a top electrode on the dielectric layer.

Abstract: A teaching tool for a robot arm for wafer reaction ovens is provided to anchor the robot arm with respect to a tray located inside a reaction oven. The teaching tool provides an upper flange for maintaining a spacing between a handle of the robot arm and a door of the oven, a position width for keeping the teaching tool aligning with a center line of the tray, and a lower tunnel aligning with the center line for allowing a blade of the robot arm to contact closely and horizontally from a lower position and thus for maintaining a position height between the blade and a floor of the reaction oven. By providing the teaching tool, easy blind calibration with multiple contact points between the robot arm and the oven can be performed so that possible efficiency down and cost up from an ill-calibration can be reduced to a minimum.

Abstract: The present invention discloses a method for fabricating a non-volatile memory structure from a single layer of polysilicon in a semiconductor substrate, wherein the semiconductor substrate with two active areas, first and second, are divided by isolation regions. In accordance with this method, a doped buried layer is formed in the first active area. Then, a first floating gate is formed on the buried layer and a second floating gate is formed on the second active area from the single layer of polysilicon. Next, two doped regions are formed at opposite sides of the second floating gate in the second active areas. Finally, a floating gate connection line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential.

Abstract: Embodiments of the present invention relate to processes utilized in the manufacturing of a semiconductor device having transistors to achieve high uniformity of threshold voltages. The invention does so by ensuring high uniformity of impurity concentration in the substrate. In one embodiment, a method for manufacturing a semiconductor device having transistors with high uniformity of threshold voltages comprises providing a substrate and a source of impurities, and disposing the substrate and the source of impurities in a first oxygen gas at a first initial temperature and heated to a first target temperature at a first temperature rate to drive the impurities into the substrate. The first initial temperature is sufficiently low to prevent the oxygen from diffusing into the substrate. The substrate is disposed in a second oxygen gas at a second initial temperature and heated to a second target temperature at a second rate to form an oxide layer on the substrate.

Abstract: A coupling for a reflectivity-measuring device connects a first shaft of a reflectivity-measuring device with a second shaft of a motor. The first shaft inserts into a first hole of a main portion of the coupling, and the second shaft inserts into a second hole of the main portion. The-main portion further comprises a third hole communicating with the first hole, a fourth hole communicating with the second hole; a first non-skid member and a second non-skid member. The first non-skid member inserts into the third hole and abuts the first shaft located inside the first hole. The second non-skid member inserts into the fourth hole and abuts the second shaft located inside the second hole.

Abstract: Embodiments of the present invention are directed to a method of reducing boron outgassing at trench power IC's oxidation process for the sacrificial oxide layer whereby the threshold voltage of the power ICs can be improved and the yield of the product can be enhanced. Nitrogen is introduced into the furnace in the entire oxidation process, including the main oxidation steps. In the preparing step of ramp up, the ramp up step and the stable step, prior to the main oxidation, nitrogen is introduced in a sufficient flow rate to make the environment near the saturated vapor pressure to reduce boron outgassing at the trench.

Abstract: In fabrication of integrated circuits, trenches (184) are formed in a dielectric (170), then a metal (e.g. tungsten or copper) is deposited. The metal (194) is removed from the top surface of the dielectric by a polishing process (e.g. CMP). The metal remains in the trenches. The inventor has discovered that the erosion of the structure in the polishing process does not strongly depend on the size of the structure. Therefore, the erosion of a large structure (440) can be estimated by measuring the erosion of a smaller test structure (450). The erosion of the test structure is measured by a probe instrument (230), e.g. a stylus profilometer or a scanning probe microscope. Use of the test structure reduces the probability of damaging the larger structure by the probe. Other embodiments are also provided.

Abstract: Embodiments of the present invention relate to a method and a system for determining an exposure time of a wafer photolithography process is applied to a wafer photolithography system and is used to determine the preferred exposure time for the L(N) batch production wafer. In one embodiment, at least three batches of the batch test wafers are recalled in a time sequence and the corresponding test values are obtained. A mean value of the test values corresponding to the at least three batches of the batch test wafers is calculated with a predetermined mathematical model. The calculated mean value is compared with a predetermined qualified examination value, and a margin value between the mean value and the qualified examination value is thus determined to adjust and generate an appropriate process exposure time. The preferred process exposure time is then employed as the exposure time of the L(N) batch production wafer.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.