Abstract: Embodiments of the present invention are directed to a metallization process for reducing the stress existing between the Al—Cu layer and the titanium nitride (TiN) layer, and solving the galvanic problem. The process does so by cooling the wafer in the vacuum apparatus where the metallization process is performed after formation of the Al—Cu layer and before the formation of the TiN layer. In accordance with an aspect of the present invention, a metallization process comprises placing a wafer in an Al—Cu sputtering chamber to form an Al—Cu layer on the wafer, and transferring the wafer to a titanium nitride sputtering chamber. An inert gas is introduced into the titanium nitride sputtering chamber to cool the wafer. A titanium nitride layer is formed on the Al—Cu layer of the wafer in the titanium nitride sputtering layer after cooling the wafer.

Abstract: The present invention provides a method and system for providing timing adjustments to perform reliable optical recording at high speeds. The present invention includes performing a timing adjustment in a coarse increment to a write control signal using a clock with a cycle less than T, where T is a fundamental unit of time for a data mark; and performing a timing adjustment in a fine increment to the write control signal using a time delay technique. The method and system in accordance with the present invention provides a write control logic which allows for multiple levels of time adjustment for each type of mark. In the preferred embodiment, a dual level timing adjustment technique is provided. The first level provides coarse timing adjustments using a clock with a cycle less than T and parameters to control the power level and time duration of each mark. The second level provides fine timing adjustments using time delay techniques.

Abstract: A heating lamp bracket for reaction chambers of evaporation coating machines. The heating lamp bracket uses paired and insulation devices to mount heating lamps to a chamber wall of a reaction chamber. The bracket includes a mounting frame that has an insulation outer surface and a mounting outer face opposing to the insulation outer surface. The insulation outer surface has at least one insulation member located thereon for fastening the mounting frame to the chamber wall. The mounting outer surface has at least two independent mounting spots for connecting respectively a connection end of the corresponding heating lamp. The independent mounting spots and non-encased type insulation members of the present invention allows for the replacement of the heating lamps and defective insulation.

Abstract: Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. A method of forming a gate oxide on a substrate comprises providing a substrate having thereon a plurality of trenches having gate oxides formed therein, wherein the plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer disposed thereon and used to form the plurality of trenches. The patterned silicon nitride layer and the patterned pad oxide layer are removed to expose a surface of the substrate as an active area of the semiconductor device. An ion drive-in to the active area on the substrate is performed by directing a flow of oxygen and nitrogen toward the substrate at a predetermined temperature and with a sufficient amount of oxygen to at least substantially prevent silicon nitride from forming on the field oxide regions.

Abstract: The present invention provides a method and system for providing a header search in a data read from an optical medium. The method includes opening a search window with a size greater than one sector; finding at least one valid header within the search window; and locating a target sector based upon the at least one valid header. The size of the window is programmable. Optionally, more than one valid header can be required to be found before they are used as the reference, for the purpose of increasing the reliability of the reference. The number of required valid headers is also programmable. Buffering of the data then begins at the target sector found based on the reference. The header of this target sector is then checked for validity. If the header is not the target, then the header search may be restarted without the need to redo the data read. The header search scheme is applicable for multiple optical data formats.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.

Abstract: The present invention provides a method and system for window realignment to correct the data frame boundaries of data from an optical media. The present invention includes: determining if a sync pattern for a data frame is within a sync window; opening an extended sync window, if the sync pattern for the data frame is not within the sync window; determining if the sync pattern for the data frame is within the extended sync window; and realigning the sync window to the sync pattern in the extended sync window, if the sync pattern is within the extended sync window. The present invention utilizes an extended sync window to realign the sync window when the number of missing sync patterns in a data stream has exceeded a threshold number. In the preferred embodiment, the width of the extended sync window and the threshold number are programmable. In this manner, the sync window can be realigned before shifting of the data renders the data uncorrectable.

Abstract: A method for determining a failure mode with the greatest effect on yield loss in a semiconductor manufacturing process is disclosed. A predetermined number of wafers are processed, and each chip on each wafer is divided into a plurality of regions with each region having a plurality of cells. Electrical tests are performed on each cell, and a region is said to have a failure mode if one cell within the region has that failure mode. The yield loss contribution of a failure mode is determined by considering the yield loss from several wafers having that failure mode as the main failure mode. The yield loss contribution of a failure mode can also be determined by considering the percentage of defective chips on a wafer having that failure mode as the main failure mode. The failure mode with the highest yield loss contribution has the greatest effect on yield loss.

Abstract: The present invention provides an integrated controller to process both optical reads and optical writes of multiple optical media. The integrated controller includes a host interface; a buffer manager coupled to the host interface; an embedded memory coupled to the buffer manager; an integrated encoding/decoding engine coupled to the buffer manager; a data channel interface coupled to the integrated encoding/decoding engine; and an integrated servo/recording processor coupled to the integrated encoding/decoding engine and the data channel interface, where the integrated servo/recording processor includes a set of write strategies. The present invention provides a controller which integrates the functionality of the conventional controllers into an integrated processor. With the controller in accordance with the present invention, a single drive may be provided which can read CD-based and DVD-based formats, read and write to Write Once Media, and read and write to Rewritable Media.

Abstract: The present invention provides a method and system for servo control in an optical drive. The method includes initiating an execution of a multiplier and accumulator controller (MAC) by a processor; and automatically calculating a transfer function by the MAC based upon a sample servo data. The present invention provides a servo control system which utilizes a MAC which is directly linked to the sample servo data. When a processor commands the MAC to execute, the MAC receives the sample servo directly from an Analog-to-Digital Converter (ADC); retrieves the corresponding accumulated sample servo data from a memory; calculates the transfer function; and stores the results back into the memory. The processor then accesses the memory to retrieve the result. Because the MAC is able to calculate the transfer function with minimal intervention from the processor, significant processing resources and time are saved.

Abstract: Embodiments of the present invention are directed to a method of reducing boron outgassing at trench power IC's oxidation process for the sacrificial oxide layer whereby the threshold voltage of the power ICs can be improved and the yield of the product can be enhanced. Nitrogen is introduced into the furnace in the entire oxidation process, including the main oxidation steps. In the preparing step of ramp up, the ramp up step and the stable step, prior to the main oxidation, nitrogen is introduced in a sufficient flow rate to make the environment near the saturated vapor pressure to reduce boron outgassing at the trench.

Abstract: Embodiments of the present invention relate to a method of making an IC capacitor. In one embodiment, the method comprises providing a substrate, forming a polycide layer on the substrate, and forming an insulating amorphous silicon layer on the polycide layer. The insulating amorphous silicon layer serves as an anti-reflection layer. The method further comprises implanting n-type ions into the insulating amorphous silicon layer to transform the insulating amorphous silicon layer into a conductive amorphous silicon layer, and patterning the polycide layer and the conductive amorphous silicon layer to form a bottom electrode on the substrate. A dielectric layer is formed on the bottom electrode and the substrate, and a conductor layer is formed on the dielectric layer. The conductor layer is patterned to form a top electrode on the dielectric layer.

Abstract: Embodiments of the present invention relate to processes utilized in the manufacturing of a semiconductor device having transistors to achieve high uniformity of threshold voltages. The invention does so by ensuring high uniformity of impurity concentration in the substrate. In one embodiment, a method for manufacturing a semiconductor device having transistors with high uniformity of threshold voltages comprises providing a substrate and a source of impurities, and disposing the substrate and the source of impurities in a first oxygen gas at a first initial temperature and heated to a first target temperature at a first temperature rate to drive the impurities into the substrate. The first initial temperature is sufficiently low to prevent the oxygen from diffusing into the substrate. The substrate is disposed in a second oxygen gas at a second initial temperature and heated to a second target temperature at a second rate to form an oxide layer on the substrate.

Abstract: Embodiments of the present invention are directed to a method of forming a bottom oxide layer in a trench on a semiconductor substrate. In one embodiment, a method for forming a bottom oxide layer in a trench on a semiconductor substrate comprises depositing an oxide layer along the surface of the sidewall and the bottom of a trench on a semiconductor substrate which has top layers, depositing a nitride layer along the surface of the said oxide layer, and forming a photo-resist filler in a trench. The top surface of the photo-resist filler is lower than the top surface of the substrate to expose a portion of the nitride layer uncovered by the photo-resist filler. The exposed portion of the nitride layer is removed to expose the oxide layer underneath. A portion of the oxide layer on the sidewalls of a trench is removed to form a bottom oxide layer in a trench.

Abstract: In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

Abstract: A tungsten-based interconnect is created by first providing a structure with an opening (464/470) in a structure and then rounding the top edge of the opening. A titanium nitride layer (150) is physically vapor deposited to a thickness less than 30 nm, typically less than 25 nm, over the structure and into the opening. Prior to depositing the titanium nitride layer, a titanium layer (140) may be deposited over the structure and into the opening such that the later-formed titanium nitride layer contacts the titanium layer. In either case, the titanium nitride layer is heated, typically to at least 600° C., while being exposed to nitrogen and/or a nitrogen compound. A tungsten layer (160) is subsequently chemically vapor deposited on the titanium nitride layer and into the opening.

Abstract: A method of prevention maintenance preventing parts of an etcher from being eroded is disclosed. First, a layer of hydrogen-free chemical compound is formed on surface of the parts of the etcher according to one embodiment of the present invention. Otherwise, the parts of the etcher are immersed into a tank containing hydrogen-free chemical compound according to another embodiment of the present invention. After that, a standard process of prevention maintenance is performed by a cleaning agent.

Abstract: The present invention provides an auxiliary tool for assembling a motor assembly to a wafer-deposition machine for supporting a wafer. The auxiliary tool facilitates easy and quick assembly of the motor assembly to the wafer-deposition machine. An aspect of the present invention is directed to an auxiliary tool for assembling a motor assembly to a wafer-deposition machine, wherein the motor assembly includes a plurality of first screw holes and the wafer-deposition machine includes a plurality of second screw holes corresponding to the first screw holes, respectively. The auxiliary tool comprises a plurality of locking members each having a substantially uniform dimension in a longitudinal direction and being configured to be inserted through one of the plurality of first screw holes of the motor assembly with a corresponding one of the plurality of second screw holes of the wafer-deposition machine to align the first screw hole with the corresponding second screw hole.

Abstract: Embodiment of the present invention are directed to improving the performance of a DMOS transistor. A method of fabricating a DMOS transistor comprises providing a semiconductor substrate having a gate oxide and a trenched gate, and implanting first conductive dopants into a surface of the semiconductor substrate adjacent to the trenched gate to form a first doping region. An insulating layer is deposited over the semiconductor substrate; and selectively etching the insulating layer to form a source contact window over a central portion of the first doping region and to leave an insulator structure above the trenched gate. The source contact window of the insulating layer has an enlarged top portion which is larger in size than a bottom portion of the source contact window closer to the first doping region than the enlarged top portion. The enlarged top portion is typically bowl-shaped.

Abstract: A system and method for low cost testing of integrated circuit devices at their rated speed during wafer probe testing while input signals to, and output signals from, the device may be operated at a lower speed. In the exemplary embodiment disclosed, a probe pad is used to enable a special test mode. When enabled, the on-chip clock generator enables a clock frequency doubler. The frequency doubler generates a 2× frequency clock from the 1× frequency external clock signals (two 1× clock phases with a 90 degree phase shift between the two clocks). The first phase of the clock uses the CLK input of the device and the second phase uses the device's CKE input.