Abstract: Embodiments of the present invention relate to a method and a system for determining an exposure time of a wafer photolithography process is applied to a wafer photolithography system and is used to determine the preferred exposure time for the L(N) batch production wafer. In one embodiment, at least three batches of the batch test wafers are recalled in a time sequence and the corresponding test values are obtained. A mean value of the test values corresponding to the at least three batches of the batch test wafers is calculated with a predetermined mathematical model. The calculated mean value is compared with a predetermined qualified examination value, and a margin value between the mean value and the qualified examination value is thus determined to adjust and generate an appropriate process exposure time. The preferred process exposure time is then employed as the exposure time of the L(N) batch production wafer.

Abstract: A nonvolatile memory array can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells of the array in parallel.

Abstract: An assembly station for a sputter shield assembly provides a work bench for assembling and disassembling the sputter shield assembly. The shield assembly has a clamp shield facing downwards to hold the shield assembly which is turned over by 180 degrees, and includes at least three bottom rim support arms for supporting the clamp shield and bearing the weight of the shield assembly, and at least three inner rim retaining arms for contacting the inner rim formed by the shield and the clamp shield. The invention provides a changed support means for holding the shield assembly on the assembly station so that one person is enough to do the assembly and disassembly of the shield assembly, and thus save manpower and operation time.

Abstract: A photoresist layer is exposed two or more times. One exposure is conducted through a regular mask, and one exposure through a modified mask with a non-clear region extending beyond a convex boundary of the non-clear region of the regular mask. The exposure through the modified mask allows one to reduce the exposure dose used with the regular mask, and thus alleviates the resist overexposure near convex areas of the non-clear pattern of the regular mask. Other embodiments are also provided.

Abstract: A power MOSFET layout according to one embodiment of the invention comprises a substrate and a plurality of cells. Each of the cells includes a base portion, a plurality of protruding portions extending from the base portion, and a plurality of photo-resist regions. Each of the cells is geometrically configured with the base portion and the plurality of protruding portions defining a closed cell boundary enclosing each of said cells. The cells are formed over the substrate, and the closed cell boundaries of the cells are arranged regularly with each other with no overlapping among the cells. The base portions are disposed in a matrix arrangement having rows and columns. The base portions are oriented from end to end in a direction of the columns and the protruding portions extend from the base portions along a direction of the rows. The photo-resist regions cover the base portions on the same column. None of the protruding portions are disposed between the base portions on the same column.

Abstract: An apparatus for forming a film on a wafer in the semiconductor process is provided. The apparatus includes an inner part containing a susceptor for mounting thereon the wafer, and an outer part covering the inner part. There are an inlet and an outlet between the inner part and the outer part and gases can flow in and out through them. A special gas-feeding pipe is partially mounted inside the inlet. The gases are ejected from the gas-feeding pipe and toward the outer part instead of the inner part. Hence, the temperature difference between the gases and the inner part is diminished and the film adhered to the inner part will not peel to form particles. It reduces the contamination problem. A gas-feeding method is also provided according to the present apparatus.

Abstract: Embodiments of the present invention are directed to providing a leakage detecting method for use in an oxidizing system of forming an oxide layer so as to shorten leakage detecting time period. In one embodiment, a leakage detecting method for use in an oxidizing system of forming an oxide layer comprises performing oxidizing processes on a plurality of test wafers in a plurality of test runs under a specified operating condition in an oxidizing system having an oxidizing chamber to form oxide layers on the test wafers having a plurality of oxide thicknesses for the plurality of test runs by flowing an oxidizing gas through the oxidizing chamber containing the test wafers. An oxygen concentration of the oxidizing gas exiting the oxidizing chamber is measured in each of the plurality of test runs.

Abstract: The present invention relates to a method for determining rapidly and accurately the polishing time of a chemical mechanical polishing process for polishing target wafers to avoid any problems of under-polishing or over-polishing. An aspect of the present invention is directed to a method for determining a chemical mechanical polishing time for removing a target polishing thickness H from an uneven surface of a target wafer. The method comprises polishing a control wafer by a chemical mechanical polishing to obtain a progressive relationship of polishing thickness and respective polishing time therefor. A first polishing time T1 is determined for removing a first thickness H1 from the target wafer, in which the first thickness H1 with substantially the uneven surface removed is smaller than the target polishing thickness H of the target wafer to be removed.

Abstract: A silicon nitride layer (120) is formed over a semiconductor substrate (104) and patterned to define isolation trenches (130). The trenches are filled with dielectric (210). The nitride layer is removed to expose sidewalls of the trench dielectric (210). The dielectric is etched to recess the sidewalls away from the active areas (132). Then a conductive layer (410) is deposited to form floating gates for nonvolatile memory cells. The recessed portions of the dielectric sidewalls allow the floating gates to be wider at the top. The gate coupling ratio is increased as a result. Other features are also provided.

Abstract: A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.

Abstract: An integrated data input sorting and timing circuit for double data rate (“DDR”) dynamic random access memory (“DRAM”) devices in which a sorting of the input data into odd/even is integrated with the necessary timing to allow synchronization with the on-chip Y-clock signal (column address select) without the need to provide separate circuits. In those devices having multiple DQS inputs, any skew between DQS pins is allowed as long as no one DQS pin violates the DQS-to-clock (“DQS-CLK”) skew requirements. The circuit and method of the present invention also allows a write to occur at command +2 cycles (last data + ½). Functionally, both rising and falling data (i.e., data on the rising and falling edges of DQS) is captured by the DQS inputs and presented in parallel to the chips internal write path and data is passed on the falling edge of DQS.

Abstract: A method is provided for advantageously etching dielectric material between highly integrated polysilicon devices with high dielectric-to-polysilicon selectivity to expose polysilicon with minimal polysilicon loss and without photoresist lift. A wet etch solution comprising surfactant and between about 0% and about 10% NH4F is used to wet etch the dielectric material and reduce polysilicon loss thickness, polysilicon resistance ratios, and polysilicon etch rates, while increasing dielectric-to-polysilicon selectivity. Advantageously, the present invention may penetrate into increasingly small geometries of highly integrated devices and may also be used for general wet etches of dielectric material in conjunction with photoresist.

Abstract: Embodiments of the present invention relate to implanting arsenic into a wafer to quickly detect if there is metal contamination, such as iron, aluminum, or manganese, on the wafer. In accordance with an aspect of the present invention, a method for detecting metal contamination of a silicon chip comprises implanting arsenic ions into the silicon chip, and etching the silicon chip with a chemical etching solution. The existence of any metal contamination is detected by observing occurrence of silicon pits on the silicon chip caused by reaction between the arsenic ions and the metal contamination and etching with the chemical etching solution.

Abstract: A memory performs a hidden refresh only at the end of a read operation or when the memory is disabled but is supposed to retain data in the disabled state. When the memory is in the enabled state, the refresh is not performed at the end of any operation other than read. This is done to ensure that execution of any memory access command will not be delayed by a refresh as long as the user follows certain timing rules. Other embodiments arc also provided.

Abstract: In fabrication of integrated circuits, trenches (184) are formed in a dielectric (170), then a metal (e.g. tungsten or copper) is deposited. The metal (194) is removed from the top surface of the dielectric by a polishing process (e.g. CMP). The metal remains in the trenches. The inventor has discovered that the erosion of the structure in the polishing process does not strongly depend on the size of the structure. Therefore, the erosion of a large structure (440) can be estimated by measuring the erosion of a smaller test structure (450). The erosion of the test structure is measured by a probe instrument (230), e.g. a stylus profilometer or a scanning probe microscope. Use of the test structure reduces the probability of damaging the larger structure by the probe. Other embodiments are also provided.

Abstract: The present invention relates to an auxiliary tool for assembling a scrubber which includes a motor, a shaft rotatably coupled to and extending through the motor, a shaft pin detachably connected to the shaft, and a disk coupled to the shaft and having a notch located relative to the shaft pin at a predetermined angle with respect to a longitudinal axis of the shaft when properly assembled. In specific embodiments, the auxiliary tool comprises a tool body configured to at least partially receive the motor, the shaft pin, the disk, and the notch of the disk. The tool body includes a first recess configured to at least partially receive the shaft pin and a protrusion configured to be at least partially received into the notch of the disk. The first recess and the protrusion are arranged at the predetermined angle to position the notch of the disk and the shaft pin of the scrubber for proper assembly at the predetermined angle with respect to the longitudinal axis of the shaft.

Abstract: Embodiments of the present invention are directed to a method of forming a bottom oxide layer in a trench on a semiconductor substrate. In one embodiment, a method for forming a bottom oxide layer in a trench on a semiconductor substrate comprises depositing an oxide layer along the surface of the sidewall and the bottom of a trench on a semiconductor substrate which has top layers, depositing a nitride layer along the surface of the said oxide layer, and forming a photo-resist filler in a trench. The top surface of the photo-resist filler is lower than the top surface of the substrate to expose a portion of the nitride layer uncovered by the photo-resist filler. The exposed portion of the nitride layer is removed to expose the oxide layer underneath. A portion of the oxide layer on the sidewalls of a trench is removed to form a bottom oxide layer in a trench.

Abstract: A thin buffer layer of SiON is formed on the top surface of the floating gate, in order to protect the polysilicon surface from attack by atomic chlorine produced during the formation of the high temperature oxide of the ONO stack. The buffer layer can also be formed on other dielectric surfaces which are otherwise subject to adverse conditions in subsequent processing, such as the nitride layer in the ONO dielectric stack.

Abstract: Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

Abstract: Embodiments of the present invention are directed to a metallization process for reducing the stress existing between the Al—Cu layer and the titanium nitride (TiN) layer, and solving the galvanic problem. The process does so by cooling the wafer in the vacuum apparatus where the metallization process is performed after formation of the Al—Cu layer and before the formation of the TiN layer. In accordance with an aspect of the present invention, a metallization process comprises placing a wafer in an Al—Cu sputtering chamber to form an Al—Cu layer on the wafer, and transferring the wafer to a titanium nitride sputtering chamber. An inert gas is introduced into the titanium nitride sputtering chamber to cool the wafer. A titanium nitride layer is formed on the Al—Cu layer of the wafer in the titanium nitride sputtering layer after cooling the wafer.