Abstract: A data select circuit for selecting a column line in a CMOS ROM and for establishing a connection between a pair of bit lines and corresponding data lines uses a single NMOS pull-down transistor on the column line and a pair of P-channel pass transistors on the bit lines, the pass transistor gates being controlled not by an inverted column decode line, but by the column line itself, thus reducing the capacative load on the column decoder and saving space.

Abstract: A differential sense amplifier employs a central region having two current paths each having a P- and N-type transistor in series, all four transistors having a common gate connection. Each input transistor has its source connected to the top of one current path and its drain connected to the bottom of the other current path, to apply the maximum differential input.

Abstract: An integrated-circuit CPU saves layout space by employing the Address Register as the Extension Register for multiplication operations, the Address Register being modified to include shifting hardware.

Abstract: A method for making a semiconductor device is described in which overlapping polycrystalline silicon layers are deposited over selected portions of a semiconductor substrate and insulated from the substrate and from each other, thereby providing an improved semiconductor device for use in a random-access memory integrated circuit.

Abstract: The power consumption and corresponding speed of an integrated circuit is scaled by means of adjusting the channel width for MOS transistors. A transistor (12) is initially fabricated with a channel (24) having a width W.sub.1. The channel (24) receives a depletion type implant (30) to make the transistor (12) lightly depleted. An enhancement implant (32) is applied to the channel (24) to cover a selected area (24a). The enhancement implant (32) is made substantially stronger than the depletion implant (30). This results in a first section (24a) of the channel (24) having a large threshold voltage while the second section (24b) of channel (24) has a relatively small pinch-off voltage. The size of the second section (24b) is selectively controlled to scale the source-drain current of transistor (12) and the corresponding power consumption of the transistor (12).

Abstract: A compact memory cell combines a volatile dynamic storage section with a shadow nonvolatile section in two vertically stacked element arrays.

Abstract: A dynamic RAM integrated circuit has improved resistance to soft errors caused by alpha particles by changing the trip-point voltage of the sense amplifier from a first value that provides resistance to bit line errors to a second, lower value that provides resistance to cell errors.

Abstract: A FIFO memory chip includes read and write pointers in the form of an X and a Y shift register carrying a pair of pointer bits that point to a memory cell in a rectangular cell array.

Abstract: An electrically erasable programmable read only memory employs a single unsteered on-chip high voltage generator that applies high voltage simultaneously to all cells on the chip.

Abstract: A MOSFET sense amplifier applies both input signals to both input transistors of a common-gate sense amplifier; each input signal being applied to the source of one input transistor and the gate of the other, thereby effectively doubling the applied input signal.

Abstract: An output driver circuit for a Mos integrated circuit eliminates the problem of charge injection into the substrate by employing a switching circuit responsive to the voltage on the output node to control the voltage drop on the output transistor.

Abstract: A nonvolatile random access memory cell (10) includes a static random access memory circuit and a corresponding nonvolatile memory circuit. The volatile memory circuit operates in a conventional manner and has first and second data states. Upon receipt of a store command signal a charge storage node is driven to either a first or a second charge state, depending upon the data state in the volatile memory circuit. For one charge state the charge storage signal is gated through a transistor (64) and a capacitor (68) to a floating gate node (44). Charge is transferred to and from the floating gate node (44) through current tunneling elements (48,50) which comprise a dielectric fabricated on a monocrystalline substrate. For the recall operation a recall command signal is applied to a transistor (52) which couples a transistor (42) to the DATA node (22) of the volatile memory circuit.

Abstract: An improved method of planarizing a level of metallization employs a trench in a smooth-surfaced dielectric and a sequence of etching steps to cut the trench locally down to the substrate, while forming the main metallization pattern at the same time.

Abstract: A method of surface hardening a metal corner includes the application of a laser beam to the surface, a portion of the beam being blocked by a cooled tube, so that the corner is heated by conduction from the heated areas.

Abstract: A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit. The method for initiating the selected functional mode comprises applying an active state of at least a first of the operational signals to the memory circuit followed by applying an active state of a second of the operational signals to the memory circuit. The timing of the second operational signal relative to the first operational signal is not within the defined specification limits of the first and the second operational signals for conventional data transfer to and from the memory. An example of the selected functional mode is the activation of circuitry (62) which serves to apply a predetermined data state to a redundant column (63) which can be substituted to replace a defective primary column within a memory array.

Abstract: A dynamic random access memory (10) is fabricated on a substrate (12) and is divided into memory sections (14, 16). Memory cells (46) are connected to bit lines (18-28, a and b), which are organized into pairs that are connected to respective sense amplifiers (34-44). A row clock circuit (52) generates clock signals to enable the addressed word line. Additional clock signals are generated by other clock circuits (56, 58). A charge pump circuit (78, 80) produces a substrate bias and includes a free running oscillator. The signal generation circuits (52, 56, 58, 78, 80) produce signal transitions which are coupled by parasitic capacitors (66-76, 81-88) into the bit lines (18-28, a and b). The clock circuits are fabricated in a symmetrical placement in relation to the bit lines (18-28, a and b) and sense amplifiers (34-44) such that the transient signals capacitively coupled from the clock circuits into the bit lines have a very low differential mode amplitude.

Abstract: A semiconductor memory circuit (140) includes a plurality of memory cells each having an access transistor (154, 158) and a storage capacitor (162, 166). The memory cells are connected to digit lines (142, 144) each of which is split into halves each connected to one input of a sense amplifier (146, 148). The sense amplifiers (146, 148) operate to pull one of the half digit lines connected thereto to ground while a pull up circuit (220) operates to elevate the other half digit line to the supply voltage. A margin test circuit receives through a control pin (236) an externally supplied test command which generates a test signal (318) to generate marginal low and marginal high voltage states to be written into the memory cells. The marginal low voltage state is generated by a voltage divider (288). The marginal high voltage state is generated by disabling the pull up circuit (220).

Abstract: A field effect transistor has improved punch-through resistance by the implantation of a dose of ions through the center of the active area. The energy of the dose is such that the ion concentration peaks at the depth most susceptible to punch-through. The threshold voltage of the transistor is set by the combination of a lower than normal threshold implant and the tail concentration of the blocking implant.

Abstract: A read only memory circuit (10) includes an array of memory transistors including a row of such transistors (12-28) connected to a common word line (30). For each column of memory transistors there is provided a set of reference transistors which receive a word line signal which is concurrent with any word line signal provided to any word line in the memory array. Column decode signals (CD1-CD4) are provided to select a memory transistor on an activated word line and to select corresponding reference transistors. The memory transistor is fabricated to have one of a plurality of threshold voltages. The reference transistors are fabricated to have different predetermined threshold voltages. The drive signals are applied through the word lines concurrently to the selected memory transistor and corresponding reference transistors to cause the transistors to transition from a first state to a second state.

Abstract: A dual-tone multi-frequency (DTMF) tone generator circuit (10) produces selected frequency row and column tones which are combined to generate a DTMF signal. Key board scan circuits (42, 44) scan a conventional push-button telephone key board to produce row and column input signals. Row and column fundamental rate signals are generated by fundamental counters (48,76) from a reference signal derived from an external crystal (12). Row and column integration rate signals are generated by integrator counters (50,78) also derived from the reference signal. Specialized row and column clock control signals (SLOPE RATE, SLOPE SIGN, AUTO ZERO) are produced by clock generators (58,82). Row and column integrators (64,92) integrate reference signals to produce discrete voltage steps at the rate of the row and column integration rate signals to produce row and column signals made up of a plurality of segments for each cycle of the signal.