Abstract: A switched-capacitor circuit (50) for passing an audio frequency over a predetermined range of frequencies fabricated on a monolithic semiconductor substrate is provided. The switched-capacitor filter (50) includes a first amplifier (60) and a second amplifier (90). A first integrator capacitor (66) is interconnected to the first amplifier (60). A second integrator capacitor (96) is interconnected to the first amplifier (90). A first input switched-capacitor (82) is interconnected between the first amplifier (60) and the second amplifier (90), such that the first input switched-capacitor (82) samples and holds the output of the second amplifier (90) during a first clock phase thereby isolating the output of the second amplifier (90) from the input of the first amplifier (60). During a second clock phase the first input switched-capacitor (82) applies the output of the second amplifier (90) to the first integrator capacitor (66).

Abstract: A circuit (10) is disclosed for use in a semiconductor integrated circuit memory. The integrated circuit memory includes row lines (102-108) which serve to activate the access transistors for memory cells (102a-108a) within the memory circuit. A row decoder circuit (36) receives a plurality of first address bits and produces a drive signal output when the decoder circuit is selected. A transition detector circuit (24) produces a transition signal whenever the state of any of the address bits is changed. A clock decoder circuit receives a plurality of second address bits together with the transition signal to produce a selected clock signal (.phi..sub.A -.phi..sub.D). The combination of the transition signal and the output of the row decoder circuit (36) serves to precharge the gate terminals of the row driver transistors (80-86) for the row lines (102-108). The selected row line receives the active state of the clock signal (.phi..sub.A -.phi..sub.

Abstract: An on-hook/off-hook detector circuit (10) is included within a telecommunications integrated circuit. A tone generator power signal (V.sub.G) is monitored as a status signal to determine when a telephone switch hook is in either an on-hook or off-hook condition. The tone generator power signal is subject to interference and transients which prevents direct utilization of it to indicate on-hook and off-hook conditions. A resistor (20) and capacitor (22) are connected externally to the circuit (10) at a junction terminal (16) to provide a time delay following a transition of the status signal (V.sub.G). The junction terminal of the resistor (20) and capacitor (22) is held at two transistor threshold voltages below the upper supply voltage (V+). At the time of transition of the status signal V.sub.G the junction terminal (16) is disconnected from a current path such that the terminal (16) is permitted to charge the capacitor (22) through the resistor (20).

Abstract: A circuit is provided for biasing the bit lines of a static semiconductor memory when each of the cells (150) within the memory is being powered by a backup power source due to failure of the primary power source. The bit lines (52) connected to the cells within the array (50) are connected to transistors (54) which bias the bit lines (52) to a high voltage upon detection of failure of the primary power for the computer. The bit lines (52) are maintained at a high voltage level to prevent discharge of a data storage node (156) through an access transistor (164) of a memory cell (150). Biasing of the bit lines (52) further prevents the integrated circuit substrate (150) from being driven excessively positive by capacitive coupling between the substrate (150) and the bit lines (52) when the primary power is restored to the circuit.

Abstract: A field effect transistor storage device for use in programmable read-only memories of the type employing a floating gate and a control gate overlying and aligned with the floating gate. An erase gate is provided adjacent at least one edge of the floating gate for removing charge stored on the floating gate. A method of electrically erasing the storage device includes holding the control gate at a fixed potential to thereby hold the floating gate at a substantially fixed potential while a relatively low voltage is applied to the erase gate to remove charge stored on the floating gate.

Abstract: A memory protect circuit (12) is provided for protecting inadvertent alteration of data stored in a data storage unit (32) of a data processing system (10). The data processing system (10) includes a microprocessor (14) for generating an address signal to selected storage locations of the storage unit (32) and for generating a key code prior to generation of the address signal. The write protect circuitry (12) includes decode circuitry (50) for receiving the key code and for generating a decoded key code. A latch (54) receives the decoded key code and generates a control signal upon receipt of the decoded key code. A NAND gate (62) receives the control signal and the address signal to generate an access signal for application to the storage unit (32) to permit alteration of data stored at a selected storage location of the storage unit (32) through a write operation.

Abstract: A charge coupled device transversal filter having split electrodes each having a sense portion and a complementary dummy portion. All electrode sense portions are coupled to a single sense line and all dummy portions are connected to a reference voltage. Tap weights are determined by relative lengths of successive sense portions and weighted samples are taken by shifting charge packets from one sense electrode position to a second while sensing the difference in displacement charge induced in successive sense electrodes. The structure is less sensitive to manufacturing tolerances than earlier structures and provides a sense signal with essentially no common mode component to a sense amplifier.

Abstract: The disclosed read only memory is formed in a two-dimensional matrix comprised of active areas disposed in parallel columns and of conductive layers disposed in rows transverse to the columns. A field-effect transistor is formed at each intersection of a column and a row. The rows of conductive layers are closely packed so that adjacent transistor channels abut one another.

Abstract: A switch for selecting internal circuit options in MOS/LSI circuits without altering the circuit layout on a semiconductor chip by selectively implanting channels of field-effect transistors such that selected circuit-option lines are coupled to a designated line. Switches may be constructed with multiple inputs and a single output, or with multiple outputs and a single input, or with multiple inputs and multiple outputs. A bidirectional switch may also be constructed by controlling the gate potential of each transistor connecting one of the option lines to the designated line with a two-input switch for selecting either a high or a low gate potential.

Abstract: A bandgap voltage reference employing only subsurface currents wich may be fabricated using a standard CMOS process. The reference includes first and second vertical bipolar transistors having common collectors formed in an integrated circuit substrate. A first resistor connects the emitter of the first transistor to ground potential. A second resistor connects the emitter of the second transistor to a reference node while a third resistor connects the reference node to ground. A differential amplifier has a positive input connected to the reference node, a negative input connected to the first transistor emitter and an output connected to the bases of the first and second transistors and also providing the reference voltage output. In a preferred form the output of the differential amplifier is buffered by a third transistor and coupled by a resistive divider to the first and second transistor bases so that the reference voltage may be selected at any scalar of the basic bandgap voltage.

Abstract: A logic circuit (20) is provided for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. Logic circuit (20) includes a voltage supply (V). A precharge transistor (30) is interconnected to the voltage supply (V) and is clocked by the first clock phase. A discharge transistor (32) is interconnected to the precharge transistor (30) thereby defining a first node (A) and is clocked by the second clock phase to conditionally discharge the first node (A). An input logic circuit (34) is interconnected to the discharge transistor (32) thereby defining a second node (B) for providing a discharge path from the first node (A) to a ground voltage potential, the input logic circuit (34) is connected to receive the input signal. An output transistor (36) is interconnected to the first node (A) for generating the delayed output signal. The output transistor (36) is clocked by the second clock phase.

Abstract: A dual-tone multiple frequency signal generator is provided for use with telecommunications systems, data transfer systems and other applications. The tone encoding system utilizes MOS/LSI integrated circuitry on a single chip powered directly by telephone line voltages. An electronic keyboard circuit provides synchronized pulses to decode single-pole, single-throw keyboard switches by row and column. A crystal-controlled oscillator generates a reference frequency which is divided according to the row and column of an activated keyboard switch to obtain two pulse signals having frequencies representative of the activated switch. The outputs of the divider circuitry are fed to a programmed logic array which generates two digitally coded signals each representing a sinusoidal waveform. A digital-to-analog ladder network converts the digitally coded signals to continuous sine waves, and an operational amplifier combines the sinusoidal waveforms to provide a dual-tone output.

Abstract: An integrated circuit memory cell (10) having a bit line (12), a word line (14) and a cell voltage supply (26) is provided. The integrated circuit memory cell (10) includes a first clock line (34) and a second clock line (36). A first transistor (20) is interconnected to the bit line (12) and the word line (14) for providing access to the memory cell (10). A second transistor (22) is interconnected to the cell voltage supply source (26) and to the first transistor (20) thereby defining a first node (S). The second transistor (22) provides a charging path from the cell voltage supply source (26) to the first node (S). A capacitor (30) is provided and interconnects the first clock line (34) and the second transistor (22). The interconnection between the capacitor (30) and the second transistor (22) defines a second node (K).

Abstract: A programmable read only memory (PROM) integrated circuit is constructed with two new operating modes: a bit-check mode and a deprogramming mode. In the bit-check mode, circuitry is provided to readily determine the apparent threshold voltage of each programmable transistor within the PROM. In the deprogrammable mode, circuitry is provided to simultaneously subject all programmable transistors within the PROM to a deprogramming stress. The bit-check mode provides a rapid programming method, and the bit-check mode and deprogramming mode are utilized in conjunction with each other to provide a rapid and thorough testing method.

Abstract: A MOSFET random access memory having an extremely low current load memory cell is disclosed. The memory cell comprises a cross-coupled binary stage in which one or more paths to ground can be selectively switched on or off through true and complement data nodes. Impedance means connect a power supply node to the data nodes for charging the data nodes to predetermined voltage levels. The impedance means comprise an intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a diffusion of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material. The impedance means is formed by an isoplanar silicon gate process as an integral portion of a polycrystalline silicon strip which interconnects the power supply node to a data node. A portion of the polycrystalline silicon strip is extended from the data node to form the gate of the transistor to which it is cross-coupled.

Abstract: A refresh counter which uses existing address buffers and is implemented with refresh address storage and decoders. The address buffers act to multiplex the refresh address storage outputs as inverted outputs when properly enabled. When all lower order bits are true at a particular unit of the refresh counter and a transfer clock signal occurs, the outputs of the buffer are transferred to the refresh storage where the buffer multiplexes them when enabled. The clocking scheme is structured to enable only at the end of a refresh cycle. In this manner, the counter is incremented at the end of each refresh cycle.

Abstract: A MOSFET random access memory having an extremely low current load memory cell is disclosed. The memory cell comprises a cross-coupled binary stage in which one or more paths to ground can be selectively switched on or off through true and complement data nodes. Impedance means connect a power supply node to the data nodes for charging the data nodes to predetermined voltage levels. The impedance means comprise an intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a diffusion of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material. The impedance means is formed by an isoplanar silicon gate process as an integral portion of a polycrystalline silicon strip which interconnects the power supply node to a data node. A portion of the polycrystalline silicon strip is extended from the data node to form the gate of the transistor to which it is cross-coupled.

Abstract: A method for operating a dynamic semiconductor memory circuit (10) having a memory cell (12) which comprises a access transistor (12a) connected to a half digit line (18) and a storage capacitor (12b). Each of the half digit lines (18, 22, 60 and 62) is charged or discharged as a result of either read operations carried out with the corresponding memory cells or write operations receiving incoming data states through input/output lines (42, 46). The charged state of the half digit line (18, 22, 60 and 62) is at a voltage substantially below that of the supply voltage of the circuit (10). After the half digit lines (18, 22, 60 and 62) are sensed and/or written to the desired states, a pullup circuit (48) for each of the half digit lines (18, 22, 60 and 62) charges the half digit lines with voltages above a predetermined threshold to the full supply voltage.

Abstract: Circuitry for automatically and selectively refreshing a dynamic node to a desired logic level. Nodes at ground potential are left at ground while nodes at an intermediate level are brought up to a supply voltage level. In a preferred use the dynamic node is a digit line in a random access memory. The circuitry includes a first transistor connected between the drain supply and a digit line having a gate connected to the source of a second transistor. The drain of the second transistor is connected to a clocked source of potential at least one threshold above the drain supply. The gate of the second transistor is precharged to a potential near the drain supply voltage preferrably concurrent with precharging of digit lines in the memory proper. A third transistor is connected between the gate of the second transistor and the digit line and has a gate connected to a clocked source of a reference potential between a digit line precharge level and the level of one threshold above ground.

Abstract: An AND-gate clock having an input stage, an output stage, and an isolation stage. The input stage receives two signals, and gates them to produce a high signal. The output stage is used to drive a load typically having a large load capacitance when both signals are true. The isolation stage isolates the input stage from the output stage when only one signal is true, therefore preventing power dissipation by current flow through the output driver stage. The isolation stage provides an alternative current path through smaller transistors, thereby incurring lesser power dissipation and requiring less layout area. A small driver stage may then be used.