Abstract: A furnace (100) is provided which aids in the reduction of polysilicon and quartz contaminants during polysilicon deposition on monocrystalline wafers. The wafers are heated for polysilicon deposition within the interior of a quartz tube (102) which is mounted so that the interior sidewalls are vertical and the tube opening is at the top of the furnace. A quartz boat (104) is adapted for carrying the wafers in a spaced apart relationship with a quartz rod (144) maintaining the wafers within the boat when it is suspended vertically from an elevator bar (128). The elevator bar moves the quartz boat vertically into the interior of the quartz tube (102) for heating without contact between the quartz boat and sidewalls of the quartz tube. The level of contamination is therefore less and the yield of certain integrated circuits much improved.

Abstract: A semiconductor dynamic memory circuit (10) includes a memory cell array (38) which includes a plurality of memory cells which are accessed through row and column lines by operation of row and column clock chain signals. A strap (68) is provided to operate the circuit (10) as either a memory which is refreshed according to internally generated addresses or a memory which is refreshed in response to externally supplied memory addresses and is easily incorporated into a memory system which utilizes error detection and correction during the refresh operation. In the absence of the strap (68) a refresh signal (20) refreshes cells of the array (38) in response to the address generated by an internal address counter (82). The circuit (10) accesses a given memory location when an externally supplied address is provided together with a RAS signal (12) and a CAS signal (16).

Abstract: A nonvolatile static random access memory cell (10) for storing data in a nonvolative state and recalling the data in its true state is disclosed. Cross-coupled transistors (12, 14) are provided having respective first and second nodes (16, 18) which are maintained at complementary logic states for volatile data storage. At least one tunnel capacitor (34), each having a floating node (36) is operatively coupled to the gate and drain terminals of one of said cross-coupled transistors (12, 14). At least one switch transistor (48) is operatively coupled to one of the first and second nodes (16, 18) and to one tunnel capacitor floating node (36). The at least one tunnel capacitor (34) and the at least one switch transistor (48) operatively coact for nonvolatile saving of volatile data stored in the cross-coupled transistors (12, 14), for recalling nonvolatile stored data in its true state to the cross-coupled transistors (12, 14), by the capacitive imbalance on the first and second nodes (16, 18).

Abstract: A method is disclosed for fabricating an isolation oxidation (44), also referred to as field oxide, to separate the active regions on the surface of an MOS integrated circuit. On the surface of a semiconductor substrate (24) there are fabricated in successive layers an oxide layer (26), a polysilicon layer (28) and a nitride layer (30). A patterned resist layer (32) is formed on the surface of the nitride layer (30). The nitride layer (30) is etched through an opening (34) in the resist layer (32), which is then removed. The isolation oxidation (44) is then grown through an opening (36) in the nitride layer (30). The isolation oxidation (44) comprises oxide derived from the oxide layer (26) and from oxide produced from the polysilicon layer (28) and the semiconductor substrate (24). Next, the nitride layer (30), the polysilicon layer (28) and the oxide layer (26) are etched.

Abstract: A buffer circuit (10) receives a TTL input signal at an input node (12) and produces an MOS logic signal at an output node (38). A capacitor (22) is precharged by a precharge signal (PC) to a high voltage state and a control node (32) is precharged to a high voltage state. An input transistor (14) receives a reference voltage which is a function of the levels of the TTL input. When the TTL input is high the transistor (14) is nonconductive thereby maintaining the charge at the control node (32) to render conductive a pull-down transistor (36) which drives the output signal at the output node (38) to a low state. When the TTL input signal goes to a low voltage state the input transistor (14) is rendered conductive by discharging a terminal of the capacitor (22). A second terminal of the capacitor (22) is driven to a lower voltage state to render conductive a discharge transistor (30) which connects the control node (32) to the node ( 24) connected to capacitor (22).

Abstract: A current supplementation circuit is designed to operate in conjunction with a two-terminal telephone line for supplying additional current to the output of a voltage regulator (42). A nonregulated voltage is received at first and second terminals (18, 20) with the nonregulated voltage comprising both DC and AC signals. An essentially regulated voltage is produced at a terminal (12) at the output of the voltage regulator (42). An essentially constant current is drawn from the first terminal (41) and provided to the second terminal (20) to provide an indication that the subscriber circuit is active. This constant current comprises first and second partial currents. The first partial current is passed through a control transistor (98) through a parasitic collector to the second terminal (14). The second partial current is passed through the control transistor (98) to the regulated voltage terminal (12) when the voltage at this terminal drops.

Abstract: A method and apparatus are disclosed for aligning an integrated circuit die (110) by use of a machine which directs a laser beam (32) downward on a wafer containing the die (110). Each die (110) is provided with one or more targets (52, 64, 78). A target (52) comprises an N+ region (56) within the target (52) and a layer of polysilicon (56) over an oxide layer (70). A laser beam (32) is scanned across the target (52) to detect a transition across an edge of a polysilicon layer (68). The transition is detected by the generation of charge carriers (36) within the region (34). The region (34) has an opposite conductivity type from that of the substrate (10) thus forming a PN junction. The PN junction is reversed biased by a voltage source (38) which is connected in series with a resistor (40) between the substrate (10) and the region (34). A center point is determined by calculating the midpoint between transitions. The establishment of a center of the target (52) establishes a reference point.

Abstract: A quiet line flip-flop is connected to a plurality of lines (12, 14) for reducing the effect of capacitive coupling between the lines (12, 14) and a line (18). A node (26) is precharged by a transistor (34) to render conductive transistors (30, 32) which connect the respective lines (12, 14) to a ground node (24). When either of the lines (12, 14) is forced to a voltage above a preset voltage the corresponding transistors (22, 28) are respectively rendered conductive to discharge the node (26) which causes the transistors (30, 32) to be rendered nonconductive thereby disconnecting the lines (12, 14) from the ground node (24).

Abstract: The input/output lines (12, 14) of a semiconductor memory device are equilibrated up until the time of the read operation by a field effect transistor (24). The source and drain terminals of the transistor are connected to the input/output lines (12, 14), and the gate is controlled by an equilibration circuit (28). The equilibration circuit (28) includes a bootstrap capacitor (40) charged to the bootstrap voltage level by the self-timing action of the equilibration circuit (28) in response to a single precharge clock signal. Feedback from the output node (26) of the equilibration circuit (28) releases a Schmitt trigger circuit to allow the capacitor (40) to be pulled to the bootstrap level by the precharge clock signal. A pump circuit (30) maintains the voltage level at the output node (26) of the equilibration circuit (28) during periods of long inactivity between column address strobes.

Abstract: A dynamic random access memory (10) receives a memory address of a row decoder (14) which charges a selected row line (18). When the row line (18) is charged an access transistor (24) in a memory cell (22) is rendered conductive to connect a storage capacitor (26) to a bit line (30). The bit lines (30, 38) are previously set at an equilibration voltage. The voltage on the bit line (30) is driven slightly above the equilibration voltage if a high voltage state had been stored in the capacitor (26) or the voltage on the bit line is driven slightly below the equilibration voltage if a low voltage state had been stored on the capacitor (26). A sense amplifier (44) is connected to the bit lines (30, 38) and upon receipt of a latch signal (L) drives the one of the bit lines (30, 38) having the lower voltage to a low voltage state. A pull-up circuit (60) drives the voltage on the remaining bit line of the pair to a high voltage state, restoring the memory storage capacitor (26) to its initial state.

Abstract: An integrated circuit memory cell pair having its data lines insulatively disposed from the semiconductor substrate at all points other than the point of electrical contact to the transistors of each memory cell. The semiconductor substrate has drain and source regions about the transmission channel of the field effect transistor and has a first capacitor electrode integral with one terminal of the transistor. A first polysilicon layer insulatively disposed from the substrate provides a conductive layer for a second capacitor electrode for each memory cell. A second insulatively disposed polysilicon layer provides the gate regions of the transistors and the data lines. The data lines make electrical contact through a self-aligned buried contact. Using this construction, a highly dense memory cell array is achieved without sacrificing capacitor area.

Abstract: A dual-tone multi-frequency (DTMF) tone generator circuit (10) produces selected frequency row and column tones which are combined to generate a DTMF signal. Key board scan circuits (42,44) scan a conventional push-button telephone key board to produce row and column input signals. Row and column fundamental rate signals are generated by fundamental counters (48,76) from a reference signal derived from an external crystal (12). Row and column integration rate signals are generated by integrator counters (50,78) also derived from the reference signal. Specialized row and column clock control signals (SLOPE RATE, SLOPE SIGN, AUTO ZERO) are produced by clock generators (58,82). Row and column integrators (64,92) integrate reference signals to produce discrete voltage steps at the rate of the row and column integration rate signals to produce row and column signals made up of a plurality of segments for each cycle of the signal.

Abstract: A read only memory (ROM) circuit (10) includes a memory storage transistor (16) which is fabricated to have one of a plurality of threshold voltages corresponding to predetermined data states. The source and drain terminals of the memory transistor (16) are connected between a column node (18) and a bit line (20). A lightly depleted data transfer transistor (30) is connected between the bit line (20) and a data line (14). The column node (18), bit line (20) and data line (14) are precharged. A memory address is decoded to drive a selected word line (12) and a selected column decode line (32) to a high voltage state. A transistor (34) discharges the column node (18). Depending upon the state of the memory storage transistor (16) the bit line (20) is discharged or maintained precharged. The state of bit line (20) is transmitted through the data transfer transistor (30) to the data line (14).

Abstract: A semiconductor memory circuit (10) has a plurality of word lines (12, 14), column lines (16, 18) and bit lines (20, 22). A memory cell transistor (30) has the gate terminal connected to the word line (12) and the drain and source terminals connected between the bit line (20) and the column line (16). A reference transistor (106) is connected to the word line (12) to provide a reference signal for input to a sense amplifier (136). A data line (54) is connected to the bit line (20) to provide the data state from the data storage transistor (30) to the sense amplifier (136). The data bit line (20) and reference bit line (104) are clamped at different pull down voltages. The memory circuit (10) includes a reference circuit that has reference transistor (106) which operates statically to provide a reference signal for the sense amplifier (136).

Abstract: A ROM circuit (10) includes a plurality of multi-bit memory storage transistors (22, 24, 26, 28, 29) and reference transistors (40, 42 and 44) all connected along a word line (16). Each of the storage transistors is provided with bit (18) and column (20) lines for activating a specific memory storage transistor and transmitting the data state thereof to sensing circuitry. A step control signal is transmitted through a control line (80) and applied to a selected one of the memory storage transistors and to each of the reference transistors (40, 42 and 44) on a selected word line (16). The step control signal is sequentially decreased in voltage to apply a progressively increasing gate-to-source voltage to each of the reference transistors (40, 42 and 44) and to a selected one of the memory storage transistors (26). The reference transistors (40, 42, and 44) are sequentially turned on by the increasing gate-to-source bias generated by the step control signal.

Abstract: A laser programmable logic switch (22) includes a fusible link (28), an output node (26) and a transistor (24) which is fabricated to be in the off state. When it is desired to have the output node (26) at a low logic state, the circuit (22) is left unchanged. But if it is determined that the output node (26) should be at a high logic level state, the fusible link (28) is opened by a first laser pulse. A second laser pulse is then applied to transistor (24) to cause damage to the structure of the transistor (24). The transistor (24) can be damaged in any of a number of modes which result in the formation of a conducting path between the output node (26) and the power terminal V.sub.cc. Unlike conventional laser switch circuits, the circuit (22) does not draw static power under any conditions thereby reducing power consumption by the integrated circuit utilizing such a laser switched gate.

Abstract: A multipin coupler (50) includes upper and lower ring members (52, 54) with a plurality of cooperating pin connections (76) surrounding central openings therethrough such that the circuitry and corresponding probe card for testing an IC chip can be interconnected through leads of the same lengths having uniform impedances. Guide pins (68) are provided to assure proper alignment of the ring members (52, 54) before engagement of the pin connections (76). A pin and slot connection supports the upper ring member (52) for limited movement relative to the lower ring member (54) for adjustability.

Abstract: An improved fixture (28) is provided for positioning components of an integrated circuit (10) during the manufacturing process. In particular, a boat (32) is provided for supporting the lead frame (18) and base (14) of an integrated circuit in a predetermined position for bonding and embedding of the lead frame to the base. A guide assembly (30) is employed with the boat (32) when positioning the lead frame and base. The lead frame is inverted and slid along a guide surface (46) into a notch (74) to abut a surface (76) of a stop pin (72). The opposite end of the lead frame abuts a second surface (80) on a stop bar (66). Diverging faces (68) on opposite sides of the guide surface center the lead frame relative to the boat and guide assembly. A base is then slid along the inside of the lead frame to abut against a second abutting surface (80) on the stop pin (72) to position the base and lead frame in a predetermined relationship.

Abstract: A burn-in tape (48) includes a backing (50) and a pair of rectangular openings (56, 58) positioned transversely on the backing (50). Power conductors (52, 54) extend longitudinally on backing (50) outboard of the openings (56, 58). Additional conductor lines (104, 106) extend longitudinally along backing (50) between the openings (56, 58). Conductor strips (62, 70, 80, 88) connect the conductors (104, 52, 106, 54) to bonding pads (12, 20, 30, 38) on an integrated circuit (10). Signal conducting strips (64, 66, 68, 72, 74, 76, 78, 82, 84, 86, 90, 92, 94, 96) extend from corresponding test pads on backing (50) to bonding pads on the integrated circuit (10). The backing (50) is provided with sprocket holes (98) for precisely aligning the burn-in tape (48) with the integrated circuit (10). The conductors on the tape (48) provide a means for operating and thereby burning-in the components of the integrated circuit (10).

Abstract: A circuit (10) is provided for use in a telecommunications integrated circuit which has a memory for storing a telephone number. The circuit (10) essentially comprises a latch having differential nodes (22, 28). The circuit (10) serves to detect when the supply voltage provided between the supply terminals (12, 14) drops to a level which causes loss of the data stored in the integrated circuit memory. An output signal (PUC) is driven to a low state upon detection of loss of power. For a slow return of supply power the nodes (22, 28) are respectively pulled to low and high states by current leakage through diodes (30, 36, 38) connected to the power terminals (12, 14). For a rapid supply voltage transition the latch node (28) is pulled high by capacitive coupling through a diode (30). This serves to set the latch in the condition where the output node (22) is at a low state to indicate loss of power. After generation of the PUC signal in the low state, external circuitry provides a reset signal (.phi..sub.