Abstract: A dynamic random access memory cell (30) includes an access transistor (32) having the gate terminal thereof connected to a word line (34) and the source and drain terminals thereof connected between a bit line (36) and a node (37). A charge storage capacitor (38) is connected between the node (37) and a decoded plate line (40). The plate line (40) receives a bi-level voltage which shifts levels in a timing sequence keyed to the word line (34) signal. Shifting of voltage levels provided to the capacitor (38) through the plate line (40) essentially doubles the signal margin of the memory circuit (30) to thereby enhance the reliability of the data stored in the memory circuit (30).

Abstract: A user-programmable and reprogrammable programmed logic array includes a self-indexing pointer to direct successive input signals to the proper cell within the array. A particular application is that of a ROM patch to correct coding errors in a ROM.

Abstract: A resistor-capacitor oscillator circuit (10) is provided and includes a voltage comparator circuit (12). A capacitor (20) is connected to an input terminal (14) of the voltage comparator circuit (12). A resistor divider network (30) is coupled to an input terminal (16) of the voltage comparator circuit (12) for generating a reference voltage. A delay circuit (50, 52) is coupled to an output terminal (42) of the voltage comparator circuit (12). A discharge device (54) is coupled to the delay circuit (50, 52) and to the capacitor (20) for discharging the capacitor (20). A switching device (40) is coupled to the output (42) of the voltage comparator circuit (12) and to the resistor divider network (30) for controlling the application of the reference voltage to voltage comparator circuit (12).

Abstract: A dynamic random access read/write memory having 4,096 binary storage cells is disclosed. The system utilizes a single set of six address input buffers and one decoder for both row and column address information. The memory array includes two 32.times.64 arrays of dynamic storage cells separated by a row of 64 sense amplifiers each having split sense buses or digit lines extending to each column of memory bits. The decoders are disposed along one edge of the array which is at right angles to the row of sense amplifiers. The column enable lines from the decoders extend through the memory array between parallel row enable lines and then turn and proceed as a different level of interconnect between parallel digit lines to select the addressed sense amplifiers. Each column enable line enables two sense amplifiers which simultaneously read data from two cells of the addressed row.

Abstract: An integrated circuit using MOSFETs having varying threshold voltages permitting improved performance and reduced area utilization on a monolithic semiconductor chip is produced by selectively varying ion implantation doses in the channels of the MOSFETs. By repeated masking and implanting steps, selected MOSFETs are implanted with differing doses of ions and combinations of doses, thereby forming circuit portions with MOSFETs having threshold voltages tailored to optimize different characteristics associated with different circuit portions.

Abstract: A clock generator circuit (10) receives an input signal PPC.0. and generates a delayed clock output signal PC.0.. The circuit (10) is set to an initial condition by a precharge signal PC.0.R prior to a transition of the input signal PPC.0.. A time delay signal is produced at a node (26) by operation of transistors (18, 28). The transition of the input signal PPC.0. produces a bootstrapped voltage at a capacitor (68). The delay signal activates a transistor (80) to couple the bootstrapped voltage to the gate terminal of an output transistor (88). The gate terminal of the output transistor (88) is driven directly from a low voltage state to a boosted high voltage state. This causes the output signal PC.0. to be driven from an initial low voltage state to the power supply voltage V.sub.cc without intervening steps. The output transistors (88, 90) of circuit (10) are never activated at the same time, thereby preventing any current spike from being propagated through the circuit (10).

Abstract: A test circuit (10) provides high and low reference voltages to a circuit (92) under test. A load (52) is connected to a multiplexed terminal (90) of circuit (92). A current source transistor (48) and a current sink transistor (132) are connected to provide current through load (52). A feedback network is connected to the current source transistor (48) and a second feedback network is connected to the current sink transistor (132). The feedback signals are compared to the reference voltages to generate control signals for driving the multiplexed terminal (90) accurately to the desired reference voltage. When the circuit (92) under test generates logic signals the load (52) sources or sinks the appropriate current depending upon the voltage states generated by the circuit (92). The voltage states generated at the multiplexed terminal (90) are transmitted through a buffer (148) to an output terminal (156).

Abstract: A nonvolatile static random access memory cell (10) includes a pair of cross-coupled transistors (12, 14) which function as a bistable circuit to store data states. Variable threshold transistors (36, 41) are respectively connected in series between the driver transistors (12, 14) and load devices (48, 50). A control node (40) is driven to a high voltage state to cause one of the variable threshold transistors (36, 41) to be driven to have a higher threshold voltage and thereby store the data state held in the cross-coupled transistors (12, 14). The data state is thus stored in nonvolatile form. Upon recall the memory cell (10) is reactivated and the threshold differential between the variable threshold transistors (36, 41) causes the driver transistors (12, 14) to be set at the stored data state. The data recalled by the memory cell (10) is in true rather than in complementary form. The variable threshold transistors (36, 41) are reset by driving the power terminal V.sub.

Abstract: A circuit for producing a compensated output signal includes a first and second stage of amplification (18) and (20) and a compensation circuit (16). The first stage of amplification (18) has a signal input, a signal output and a control input. The second stage of amplification (20) also has a signal input, a signal output and a control input with the signal input of the second stage (20) connected to the signal output of the first stage (18). A passive feedback network comprised of a series connected resistor (R.sub.F) and capacitor (C.sub.F) is connected between the signal input and the signal output of the second stage (20). The combination of the passive feedback network, the first stage (18) and the second stage (20) provide a gain and frequency response that is defined by three poles and one zero. The zero overlaps one of the poles thereby providing an extended frequency response. The passive feedback network varies the frequency response in response to manufacturing process variations.

Abstract: A compensation circuit (10) controls the gain of transmit and receive amplifiers (47), (49) as a function of a residual input current (I.sub.res). Circuit (10) includes a constant current source (24) which is connected to produce mirrored constant currents in transistors (26) and (28). The residual current is passed through a resistor (R.sub.loop) to produce a reference voltage. The constant current from the transistor (26) is divided with the first part of the current passing through the resistor (R.sub.loop) and the second part of the current passing through a resistor (50) and a transistor (54). The transistor (54) is connected in a mirror configuration with a transistor (58). When the residual current increases, the current mirrored to transistor (58) decreases. A transistor (32) is connected in parallel with the transistor (58) to receive the remaining current from the transistor (28) which is not drawn by the transistor (58).

Abstract: A power supply control circuit (20) selectively provides power to an integrated circuit from either a primary power supply terminal (22), or through terminals (24, 26) connected to backup batteries. The voltage level of the primary power is monitored continuously and when it drops to a predetermined level one of the two backup batteries is substituted to power the integrated circuit in a power-down mode. The circuit (20) includes a level detector circuit (32) and a voltage reference circuit (98). In the power-down mode one battery is connected to power the integrated circuit and this battery is continuously monitored. When the voltage of the on-line battery drops to below a fixed level in comparison to off-line battery a control logic circuit (92) activates switches (56) to substitute the off-line battery for the on-line battery. Control logic circuitry (92) is provided to disconnect the control signals from the integrated circuit to prevent loss of stored information.

Abstract: A microcomputer circuit is described for carrying out bit operations between registers and ports without the need for bit testing followed by branch operations. The microcomputer includes a bus (10) connected to provide communication to an ALU (22), registers (11, 12) and a serial port (13). A bit test circuit is connected to the bus (10) and provides a selected bit to a temporary carry storage (18) which in turn transfers the selected bit to a carry flag location (28a) within a status register (28). Instruction codes are input to an instruction register (32) which provides operating commands to an entry ROM (36) and an ALU control circuit (40). After a bit test operation is completed and in response to a copy or exchange instruction provided to the instruction register (32) a bit can be copied from one register to another register, bits can be exchanged between two registers or bits within a register can be parallel-to-serial converted and provided to the serial port (13).

Abstract: A method of forming a plurality of interconnected metal oxide semiconductor field effect transistors on P-type semiconductor substrate (10). A layer of oxide (14) is formed on the substrate (10) and then a polysilicon layer (16) is formed on top of the oxide layer (14). A layer of silicon nitride (18) is deposited on top of the polysilicon layer (16). The silicon nitride layer (18), polysilicon layer (16) and oxide layer (14) are selectively etched to form a conductor pattern. The conductor pattern defines a gate electrode and a plurality of interconnecting lines (42) that interconnect transistors to each other and to the peripheral circuits that drive the transistors. The source and drain regions (26 and 28) are ion implanted with arsenic ions. The exposed sidewalls of the polysilicon layer (16) are oxidized lateral and subjacent to the silicon nitride layer (18).

Abstract: A tone synthesizer circuit (10) includes a multi-tap resistor (86) which produces a plurality of discrete voltages at the taps (T1-T16). A switch (88-118) is provided for each of the taps (T1-T16). The tap switches (88-118) are organized into four groups. A second group of switches are organized into two groups with each of the second switch groups having a connection to one of the switches in each of the first groups. A third group of switches (164-170) are each connected to one of the group of the second switches (132-138). Circuitry responsive to a digital clock input signal produces a group of control signals on control lines (66-72) which are respectively connected to operate each of the four groups of the first switches (88-108). Further circuit means responsive to the digital input signal transmit control signals through control lines (74-76) to operate the second group of switches (132-138).

Abstract: A sidetone circuit (44) is connected to the terminals of a two-line telephone system. The sidetone circuit (44) receives inputs from a DTMF source (62) and a microphone (72). These inputs are selectively passed through a circuit (82) to produce a modulating signal which controls a current source (46) and a current (54). The current source (46) is connected between the telephone line terminals. The input audio signal from the microphone (72) modulates the current source (46) to impress a voltage upon the telephone line. The current source (54) is connected between a first of the telephone lines and a balance node (60). A resistor (58) is connected between the balance node and the second of the telephone lines. An incoming audio signal over the telephone line is coupled to the balance node (60) for summing with an inverted audio signal. The input audio signal from the microphone (72) is further coupled to the balance node (60).

Abstract: An improved integrated circuit package (10) includes a cover (12), an intermediate subassembly (14) and a bottom subassembly (16). The intermediate and bottom subassemblies (14, 16) include lead frames (48, 22) respectively embedded therein, as well as openings which define a cavity for a semiconductor chip. The external lead pins (24) of the bottom subassembly (16) permit interconnection of the package with a circuit board or the like, while the external contacts (50) of the intermediate subassembly (14) cooperate with openings (62) in the cover to provide integral socket connections for other semiconductor packages or electrical components.

Abstract: A low loop current switch latch circuit (10) monitors a residual current which is derived from a telephone line and is proportional to the current drawn by a telephone subscriber circuit. Bipolar transistors (20, 26) are connected to produce a proportional current to the residual current. A current mirror circuit includes a master transistor (30) and a slave transistor (32). The proportional current is drawn through the master transistor (30). The current produced by the slave transistor (32) is provided to a node (33). A constant power source (36) provides a constant current to a node (39). A pair of cross-coupled transistors (40, 46) are connected to the nodes (33, 39) such that the cross-coupled transistors are set to first and second states as a function of the current derived from the slave transistor (32).

Abstract: A semiconductor memory having an address buffer (10), row decoder (12), word lines (16), bit line (20) and sense amplifier (22) for accessing individual memory cells in an array of memory cells. In order to emulate worst case delays experienced in the word lines in accessing the last cells in the rows in order to prevent the sense amplifiers (22) from reading the bit lines (20) too soon, a tunable delay circuit (30) delays actuation of the sense amplifier. This circuit is divided into a plurality of impedance section with associated parasitic capacitance where groups of sections are bypassed by switching devices such as MOS transistors. The delay of a signal propagating through this tunable delay circuit can be varied by bypassing varying numbers of the sections with the switching devices.

Abstract: A compensated current reference circuit (10) includes bipolar transistors (32, 48) which have corresponding base-to-emitter resistors (36, 52). A bipolar transistor (70) and associated circuitry produces a variable amplitude tail current which has a predetermined temperature coefficient and regulates the current flow through the bipolar transistors (32, 48). The combination of tail current for the transistor (48) and the impedance size of its corresponding resistor (52) are adjusted to produce a reference current through a transistor (44) which has a relatively large negative temperature coefficient. The bipolar transistor (32) and its associated base-to-emitter resistor (36) together with the tail current through transistor (38) are adjusted such that a current through transistor (22) is produced which has a relatively small negative temperature coefficient.

Abstract: A margin test circuit (10) is provided for a semiconductor memory circuit having a plurality of memory cells (16). Each of the memory cells (16) in one row of cells (16) are interconnected to a word line (14). The margin test circuit (10) further includes a row decoder/driver (12) which receives a variable voltage (V.sub.cc *) for changing the signal level stored within a memory cell (16) to thereby determine the marginal voltage level at which the memory cell (16) will maintain storage of a signal level. The variable voltage (V.sub.cc *) is the semiconductor memory circuit main supply source (V.sub.cc) in normal operation but can be forced to a different voltage during the margin test.