Patents Assigned to Murata Manufacturing Co., Ltd.
  • Patent number: 10097148
    Abstract: Provided is a power amplification module that includes: a first amplification circuit that amplifies a first signal and outputs the amplified first signal as a second signal; a second amplification circuit that amplifies the second signal and outputs the amplified second signal as a third signal; and a feedback circuit that re-inputs/feeds back the second signal outputted from the first amplification circuit to the first amplification circuit as the first signal. The operation of the first amplification circuit is halted and the first signal passes through the feedback circuit and is outputted as the second signal at the time of a low power output mode.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: October 9, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shota Ishihara
  • Patent number: 10098238
    Abstract: A method of manufacturing a resin multilayer substrate is provided in which a component (3) is incorporated in a stacked body obtained by stacking a plurality of thermoplastic resin sheets (2). The method includes the steps of: softening a first resin sheet (2a) by heating, and pressing the component (3) against the first resin sheet (2a), thereby fixing the component (3) to the first resin sheet (2a); stacking the first resin sheet (2a) on a second resin sheet (2b) having a through hole (14) receiving the component (3) and a third resin sheet (2c) located adjacent to a lower side of the component (3) such that the component (3) is inserted into the through hole (14) and the lower surface of the component (3) faces the third resin sheet (2c); and performing compression bonding by heating and pressurizing the stacked body including these resin sheets (2).
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: October 9, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masaki Kawata, Yuki Ito
  • Patent number: 10096901
    Abstract: A coil module includes a substrate layer, a coil electrode, and a sealing resin layer. The coil electrode includes metal pins that stand on a resin substrate of the substrate layer in such a way that lower end surfaces thereof are exposed on a lower surface of the substrate layer. The sealing resin layer is stacked on the substrate layer and covers the metal pins. Upper end surfaces of the metal pins are exposed on an upper surface of the sealing resin layer. Each of the metal pins and a corresponding one of the metal pins paired therewith are connected to each other on the lower surface of the substrate layer through a lower wiring pattern. Each of the pins and a corresponding one of the metal pins are connected to each other on the upper surface of the substrate layer through an upper wiring pattern.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: October 9, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shinichiro Banba
  • Patent number: 10097157
    Abstract: A crystal vibrating device that includes a crystal resonator mounted on a substrate by a first conductive adhesive layer and a second conductive adhesive layer, and, when the first conductive adhesive layer and the second conductive adhesive layer are viewed in a plan view, the first conductive adhesive layer and the second conductive adhesive layer each have a) a planar shape in which two circles or ellipses are partly superimposed upon each other, b) two conductive adhesive layer portions that are separated from each other, or c) a length direction and an aspect ratio, which is a ratio between a maximum size in the length direction and a maximum size in a width direction that is orthogonal to the maximum size in the length direction, is in a range of 1.5 to 3.0.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: October 9, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Bunta Okamoto, Motoyoshi Sakai
  • Patent number: 10096812
    Abstract: A battery is provided. The battery including a positive electrode that includes a positive electrode current collector and a positive electrode active material layer provided on the positive electrode current collector; a negative electrode; and a separator that includes at least a porous film; wherein the porous film satisfies the following equations: 0.04?Ri??0.07L?0.09×S+4.99 Ri=?2L/?? ??=[{(L?/100)?Rz×0.46/3}/L]×100 ?={(1.216×?Td×10?4)/L}0.5 where Ri represents a film resistance (?m), L represents a film thickness (?m), ? represents a tortuosity factor, T represents air permeability (sec/100 cc), d represents a pore size (nm), Rz represents a surface roughness maximum height (?m), ? represents a porosity (%), ?? represents a corrected porosity (%), and S represents an area density of the positive electrode active material layer (mg/cm2).
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: October 9, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tomohiro Abe, Kentaro Takagi
  • Patent number: 10096763
    Abstract: An elastic wave device includes elastic wave elements, each including a piezoelectric layer directly or indirectly supported by a supporting substrate and an electrode disposed in contact with the piezoelectric layer, and a highly heat-conductive member stacked on a surface of the supporting substrate, opposite to the surface supporting the piezoelectric layer, in which the thermal conductivity of the supporting substrate is higher than the thermal conductivity of the piezoelectric layer, the coefficient of linear expansion of the supporting substrate is lower than the coefficient of linear expansion of the piezoelectric layer, the highly heat-conductive member has a larger area than the surface of the supporting substrate supporting the piezoelectric layer, and the thermal conductivity of the highly heat-conductive member is higher than that of the piezoelectric layer.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: October 9, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takashi Iwamoto
  • Patent number: 10096427
    Abstract: The electronic component includes a substantially rectangular parallelepiped multilayer body formed by laminating a plurality of insulation layers, a capacitor including a plurality of capacitor conductor layers provided on the insulation layers, and a substantially spiral-shaped inductor including one or more inductor conductor layers provided on the insulation layers and having a center axis extending along the lamination direction. A mounting surface of the multilayer body is a surface of the multilayer body located on the end of one side of a first orthogonal direction orthogonal to the lamination direction. The inductor conductor layer and the capacitor conductor layer are provided on the first insulation layer. On the first insulation layer, an end portion of the capacitor conductor layer on the one side of the first orthogonal direction are closer to the mounting surface than an end portion of the inductor conductor layer on the one side of the first orthogonal direction.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: October 9, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Masayuki Yoneda
  • Patent number: 10098229
    Abstract: To provide a compact module that is capable of achieving a low profile and that has excellent high-frequency characteristics, a module includes a parent board; first and second child boards arranged so as to face the parent board; multiple electronic components that include first electrodes and second electrodes electrically connected to the first electrodes, respectively, on both opposing faces, the first electrodes being connected to the first child board, the second electrodes being connected to the parent board; and multiple electronic components that include first electrodes and second electrodes electrically connected to the first electrodes, respectively, on both opposing faces, the first electrodes being connected to the second child board, the second electrodes being connected to the parent board.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: October 9, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoichi Takagi, Tadashi Nomura, Masato Yoshida, Nobuaki Ogawa, Mitsuhiro Matsumoto
  • Patent number: 10095644
    Abstract: Provided is a data transfer device that reduces generation of noise caused by an unnecessary transfer of a serial clock signal. The data transfer device includes: a clock generator circuit that generates a second serial clock signal, the second serial clock signal being synchronized with a first serial clock signal transmitted from a master device; a determination circuit that determines whether a request from the master device is addressed to the data transfer device or not; and a data processing circuit that operates by receiving a transfer of the first serial clock signal from the clock generator circuit on condition of the request from the master device being determined to be addressed to the data transfer device.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: October 9, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuhiro Nakamuta, Yuji Shintomi, Satoshi Matsumura, Masanori Iijima
  • Patent number: 10094871
    Abstract: An electronic-component testing device capable of achieving efficient heat-releasing from a self-heating electronic component and efficiently performing a desired test while maintaining the temperature of the electronic component in a predetermined range higher than ordinary temperature.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 9, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masakazu Itakura, Tetsuo Kawasaki
  • Patent number: 10094993
    Abstract: A connector and a connector set that can be fabricated by using a mold including a smaller number of components.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 9, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Ryo Watanabe
  • Patent number: 10090109
    Abstract: A monolithic ceramic capacitor includes a plurality of first and second inner electrodes in a ceramic body. A direction in which the first and second inner electrodes are stacked is a stacking direction, a direction perpendicular or substantially perpendicular to the stacking direction in the ceramic body is a length direction, and a direction perpendicular or substantially perpendicular to the stacking direction and the first direction is a width direction. The ceramic body includes an effective portion, a first outer layer portion, a second outer layer portion, a first side portion, and a second side portion. A ratio A/B is about 0.04 or less when a dimension of each of the first side portion and the second side portion in the width direction is A and a dimension of the effective portion in the stacking direction is B.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: October 2, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yukihiro Fujita, Tadateru Yamada
  • Patent number: 10090096
    Abstract: A common mode choke coil includes a laminated-type coil that has high breakdown voltage reliability. Coil conductors and a coil conductor for a secondary coil are laminated so as to be respectively interposed between, coil conductors for a primary coil, two coil conductors connected to each other by an inner circumferential side via hole conductor and two coil conductors connected by an inner circumferential side via hole conductor. Meanwhile, in the primary coil, an outer circumferential side via hole conductor is provided so as to pass through only one insulation layer, and accordingly, a length of the outer circumferential side via hole conductor in an axis line direction thereof is reduced. As a result, an amount of conductive material used for the outer circumferential side via hole conductor that diffuses during firing can be reduced, and a drop in a thickness of the insulation layers can be suppressed.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: October 2, 2018
    Assignee: Murata Manufacturing Co., Ltd
    Inventor: Masaki Inui
  • Patent number: 10090108
    Abstract: A multilayer ceramic capacitor having an external electrode with a glass phase, where an occupation rate of the glass phase is 30% to 60% on an area ratio, and a maximum length c of the glass phase is 5 ?m or less.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: October 2, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tetsuya Kisumi, Toshiki Nagamoto, Yasuhiro Nishisaka, Yoko Okabe
  • Patent number: 10090268
    Abstract: A solder bump formed on an Ni electrode with the use of a solder ball containing Bi as a main component and Sn as a sub component. The solder ball contains Sn from 1.0 to 10.0 mass % and at most 1.0 mass % of at least one of Cu and Ag. A solder joint portion obtained by use of the solder bump has at least one of Sn and an SnBi eutectic alloy.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: October 2, 2018
    Assignees: MURATA MANUFACTURING CO., LTD., SENJU METAL INDUSTRY CO., LTD.
    Inventors: Yasuyuki Sekimoto, Hidekiyo Takaoka, Shigeo Nishimura, Minoru Ueshima, Tohru Kurushima
  • Patent number: 10089502
    Abstract: An accessory device to be mounted on a main device is provided with a wireless IC device. The main device is provided with a reader/writer that is an interrogator that communicates with the wireless IC device of the accessory device. When the accessory device is mounted on or about to be mounted on the main device, the reader/writer selects two or more frequencies in a frequency band in which an authentic wireless IC device can communicate to perform communication with the wireless IC device. With this configuration, even if the identification code written in an RFID tag is read and the RFID tag is duplicated, the duplicated RFID tag can be accurately and effectively determined as being counterfeit.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: October 2, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Noboru Kato, Satoshi Ishino
  • Patent number: 10090823
    Abstract: An elastic wave resonator includes series divided resonators on a piezoelectric substrate, first and second outer busbars, a first interstage busbar, first to fourth electrode fingers and first and second dummy electrode fingers. Third dummy electrode fingers are not provided at at least one of a side where the second electrode fingers are provided and a side where the third electrode fingers are provided or third dummy electrode fingers having a length smaller than lengths of the first and second dummy electrode fingers are provided at at least one of a side where the second electrode fingers are provided and a side where the third electrode fingers are provided. The third electrode fingers are arranged on an extension to which the second electrode fingers extend.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: October 2, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takuma Kuzushita
  • Patent number: 10090824
    Abstract: A filter apparatus includes a plurality of stages of ladder circuits connected between an input terminal and an output terminal, and a band width ratio is about 4.3 % or higher. The ladder circuits of respective stages include series arm resonators, parallel arm resonators, first inductors respectively connected between a ground potential and first end portions, and second inductors respectively connected between the ground potential and second end portions.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 2, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Norihiko Nakahashi
  • Patent number: 10091886
    Abstract: In an LC composite component, a chip capacitor is built in a multilayer substrate including base material layers made of a thermoplastic resin. The number of the base material layers in a portion overlapping the component as seen from a lamination direction is equal to the number of the base material layers in a portion around the component as seen from the lamination direction. Wiring patterns that adjust the thickness of the multilayer substrate are provided around the chip capacitor as seen from the lamination direction, and on principal surfaces of the base material layers, so as to surround the chip capacitor.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: October 2, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kosuke Nishino, Kuniaki Yosui
  • Patent number: D830348
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: October 9, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kaoru Sudo, Michiharu Yokoyama, Hideki Ueda, Ryuken Mizunuma, Masayuki Nakajima