Patents Assigned to N/A
  • Patent number: 12063700
    Abstract: Thus there is provided a method and appropriately arranged devices for configuring for communications in a wireless network comprising performing a configuration protocol, and sending by the enrollee device, during an execution of the configuration protocol, a message containing an indication of a status of a previous configuration attempt. A configuring device receiving the status of the previous configuration attempt is then able to act upon it and inform the user that a previous attempt failed. The information provided to the user would allow the user to understand why the device fails to connect to the desired network and perhaps alert them to the fact that it has not connected.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: August 13, 2024
    Assignee: Koninklijke Philips N.V.
    Inventor: Johannes Arnoldus Cornelis Bernsen
  • Patent number: 12062194
    Abstract: According to an aspect, there is provided an imaging system (1) for imaging of subjects.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: August 13, 2024
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Erik Gosuinus Petrus Schuijers, Rieko Verhagen, Jonathan Palero
  • Publication number: 20240266425
    Abstract: The present disclosure relates to a method of forming an HEMT transistor, comprising the following successive steps: a) providing a stack comprising a semiconductor channel layer, a semiconductor barrier layer on top of and in contact with the semiconductor channel layer, and a semiconductor gate layer arranged on top of and in contact with the semiconductor barrier layer, the semiconductor gate layer comprising P-type dopant elements; and b) compensating for the P-type doping with oxygen atoms, in an upper portion of the semiconductor gate layer, by an oxygen anneal, so as to define a PN junction at the interface between the upper portion and a central portion of the semiconductor gate layer.
    Type: Application
    Filed: January 25, 2024
    Publication date: August 8, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Aurore CONSTANT, Ferdinando IUCOLANO, Cristina TRINGALI, Maria Eloisa CASTAGNA
  • Publication number: 20240264844
    Abstract: In a method of emulation of N boot programs in a memory, N being an integer greater than 2, the size of a no-access region of the memory containing the boot programs is increased in response to execution of each boot program.
    Type: Application
    Filed: February 2, 2024
    Publication date: August 8, 2024
    Applicant: STMicroelectronics International N.V.
    Inventor: Jawad BENHAMMADI
  • Publication number: 20240264831
    Abstract: Various methods, apparatuses/systems, and media for automatically determining whether an application is SRE ready for production deployment are disclosed. A processor implements an AI/ML algorithm and natural language processing algorithm to analyze input data corresponding to an application onboarded onto an application platform; generates an assessment report data that includes SRE readiness score that identifies SRE maturity for the application based on analyzing the input data; determines whether the generated SRE score is equal to or more than a preconfigured assessment score or less than the preconfigured assessment score; automatically determines that the application is SRE ready for production deployment based on determining that the generated SRE score is equal to or more than a preconfigured assessment score; and automatically implements a self-healing algorithm to correct each deficiencies identified in the assessment report.
    Type: Application
    Filed: March 20, 2023
    Publication date: August 8, 2024
    Applicant: JPMorgan Chase Bank, N.A.
    Inventors: Harish PADMANABAN P C, Karthikeyan CHANDRASEKARAN, Raghavendra Venkata CHIDELLA, Ganapathi NATARAJAN, Kiran GADDALA
  • Publication number: 20240266343
    Abstract: An integrated circuit includes a semiconductor substrate patterned to include a first semiconductor track and a second semiconductor track separated from each other by a trench isolation region. The integrated circuit includes a logic circuit including a transistor having a first drain subregion in the first semiconductor track, a second drain subregion in the second semiconductor track, a first source subregion in the first semiconductor track, and a second source subregion in the second semiconductor track. A diffusion bridge of semiconductor material extends between the first and second semiconductor tracks and connects the first source subregion to the second source subregion. The first drain subregion and the second drain subregion are electrically connected by a drain metalization.
    Type: Application
    Filed: January 19, 2024
    Publication date: August 8, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Anuj BHARDWAJ, Anand Kumar MISHRA, Rohit Kumar GUPTA
  • Publication number: 20240264894
    Abstract: Various methods, apparatuses/systems, and media for improving SRE observability are disclosed. A processor defines a schema in a common manner; causes any application included across a distributed set of applications to utilize the schema to describe an error associated with a downstream application such that root failing component associated with the error is always at a bottom error frame in a response; implements a common structure for distributed error propagation in a chain of applications across the distributed set of applications in connection with the error message; generates error logs received from the chain of applications; stores the error logs in a centralized location accessible by all SRE users and application owners; calls a corresponding application programing interface (API) to access the error logs from the centralized location for utilizing in remediation.
    Type: Application
    Filed: February 2, 2023
    Publication date: August 8, 2024
    Applicant: JPMorgan Chase Bank, N.A.
    Inventors: Mahesh NAPA, Gordon Robert MACDONALD, Mark Leslie GIBBONS
  • Publication number: 20240264517
    Abstract: A multi-zone illumination system includes a light source formed by first emitters configured to transmit a first light signal having a first polarization state and second emitters configured to transmit a second light signal having a second polarization state transverse to the first polarization state. An optic receives the first light signal and generates a first structured illumination of a first far field zone. The optic further receives the second light signal and generates a second structured illumination of a second far field zone. The first and second far field zones are offset from each other.
    Type: Application
    Filed: February 7, 2023
    Publication date: August 8, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Enrico Giuseppe CARNEMOLLA, Brandon Scott JOHNSON
  • Publication number: 20240261346
    Abstract: The present invention relates to nutritional compositions comprising non-digestible oligosaccharides and beta-casein comprising at least 75% by weight of a beta-casein variant having a proline at position 67 of the beta-casein amino acid sequence for use in improving gut microbiota of an infant or child, wherein improvement of gut microbiota encompasses increasing Lactobacillus levels. Advantageously, the composition further favors the increase of Bifidobacterium levels and inhibits the growth of opportunistic and/or pathogenic bacteria.
    Type: Application
    Filed: April 18, 2024
    Publication date: August 8, 2024
    Applicant: N.V. Nutricia
    Inventors: Cornelus Johannes Petrus Van Limpt, Joost Willem Gouw, Jan Knol, Sebastian Tims, Kaouther Ben Amor
  • Publication number: 20240264905
    Abstract: EEPROM emulation is provided in a phase-change memory of a circuit integrating a microprocessor. A granularity for writing into lines of the phase-change memory is defined according to a size of data packets to be written. A first error correction code calculated by a program executed by said microprocessor is associated with each data packet. Several data packets and their associated first error correction codes are then stored in a same line of the phase-change memory data packet.
    Type: Application
    Filed: February 1, 2024
    Publication date: August 8, 2024
    Applicant: STMicroelectronics International N.V.
    Inventor: Jawad BENHAMMADI
  • Publication number: 20240266996
    Abstract: A hatch configured to be placed in an operative position thereof over a storage space in a removable or displaceable manner, e.g. over a cargo hold of an inland waterway cargo vessel, the hatch having a width and a length, and the hatch being configured to be supported at each one of opposed sides thereof seen in direction of the width of the hatch by a support structure, the hatch in the operative position covering the storage space directly underneath. A surface area of the hatch is provided with photo-voltaic cells. The hatch includes, integrated therewith, a power converter system connected to the photo-voltaic cells and configured to convert the electrical energy entering the converter system into another output form of electricity, the power converter being connectable, e.g. via an electrical connector integrated with the hatch, to a grid and/or a remote consumer of the outputted electricity.
    Type: Application
    Filed: May 30, 2022
    Publication date: August 8, 2024
    Applicant: Blommaert N.V.
    Inventors: Tom BLOMMAERT, David Michel KESTER, Kasper KEIZER, Flip ALKEMADE
  • Publication number: 20240267217
    Abstract: A method is presented for verifying a writing of a key into a non-volatile memory. A first cyclic redundancy code of the key is stored into a register of an interface of the memory. A second cyclic redundancy code is computed on a message formed by the copied key having the first cyclic redundancy code linked thereto. The writing of the key into the non-volatile memory is considered as valid when the second cyclic redundancy code is equivalent to the zero value.
    Type: Application
    Filed: February 2, 2024
    Publication date: August 8, 2024
    Applicant: STMicroelectronics International N.V.
    Inventor: Jawad BENHAMMADI
  • Publication number: 20240267214
    Abstract: Systems and methods for securely sharing and authenticating a last secret can include generating, by a cryptographic module on a first network node, a seed configured for deriving or recovering a last secret, the last secret providing access to a secure entity and being a last cryptographic element controlling access to the secure entity, creating, by the cryptographic module, an envelope for the seed, enveloping the seed by the envelope, and transmitting, by the cryptographic module, the seed to a computing system on a second node different than the first node, the computing system being configured to decrypt the envelope of the enveloped seed to recover the seed, and obtain the last secret based on the seed, where the cryptographic module is prevented from deriving the last secret.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 8, 2024
    Applicant: Wells Fargo Bank, N.A.
    Inventors: Phillip H. Griffin, Jeffrey J. Stapleton
  • Publication number: 20240265109
    Abstract: A processor of a processing device executes a boot code to carry out a boot sequence of the processing device. The execution includes at least one verification step for verifying a proper progress of the boot sequence. When the verification step identifies an error in the progress of the boot sequence, a status value (with an indication that an error occurred during that verification step) is stored in a register of the processing device. The processing device is then reset. The register is accessible in read mode via a debugging interface of the processing device.
    Type: Application
    Filed: February 6, 2024
    Publication date: August 8, 2024
    Applicant: STMicroelectronics International N.V.
    Inventor: Gilles TROTTIER
  • Publication number: 20240266423
    Abstract: The present disclosure concerns a method of forming an electronic power component inside and on top of a semiconductor substrate, comprising the following successive steps: a) forming of a peripheral groove in the semiconductor substrate on the side of a first surface of the semiconductor substrate; b) deposition of an oxygen-doped polysilicon layer, on top of and in contact with the bottom and the lateral walls of the peripheral groove and with the first surface of the semiconductor substrate; c) local deposition of a glass layer, on the oxygen-doped polysilicon layer, the glass layer extending in the peripheral groove and further extending over a portion of the first surface of the semiconductor substrate; and d) etching of the oxygen-doped polysilicon layer so that it extends on the first surface of the semiconductor substrate beyond the glass layer.
    Type: Application
    Filed: January 23, 2024
    Publication date: August 8, 2024
    Applicant: STMicroelectronics International N.V.
    Inventor: Benjamin MORILLON
  • Patent number: 12053108
    Abstract: A cover (12) is configured to be used with a liquid container for realizing a drinking device in conjunction with the liquid container. The cover (12) is particularly designed to prevent fluid communication therethrough in a default condition, and to allow fluid communication therethrough in an actuated condition. To that end, the cover (12) includes a gasket (30) and a cover body (20) accommodating the gasket (30), the cover body (20) comprising a liquid passage area (21) and a sealing rim (22). In order for the cover (12) to be leakproof to a high extent under all circumstances in which it is not desired to retrieve liquid through the cover (12), the gasket (30) has at least one structural feature (34) configured to secure sealing contact of the gasket (30) to the sealing rim (22) of the cover body (20) in the default condition of the cover (12).
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: August 6, 2024
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Christoph Dobrusskin, Amir Masoud Akbari Pazooki, Narasimha Shastri, Coen Petrus Martinus Claassen
  • Patent number: 12056688
    Abstract: A mobile device includes a processing circuit to perform operations including transmitting a device token and a customer token to a computing system, the device token identifying the mobile device and a first session of a client application, the customer token identifying a user. The operations can include enabling access to the client application during the first session based on the device token and the customer token and receiving a second device token, the second device token identifying the mobile device and a second session. The operations can include receiving, during the first session, an identification number associated with an account of the user for a transaction, the identification number generated in response to a fund request from the mobile device. The operations can include providing a user interface displayed on the mobile device during the first session and receiving during the first session, an approval for the transaction.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: August 6, 2024
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Ashish Bhoopen Kurani, Nikolai Stroke, Bipin Sahni, Stephen M. Ellis, Steve Puffer
  • Patent number: 12055989
    Abstract: An integrated circuit includes a plurality of flip-flops and a global reset network for resetting the flip-flops. The integrated circuit includes a synchronous clock delay circuit that delays, responsive to a global reset signal, a transition in a clock signal provided to the flip-flops. The delay in the transition of the clock signal ensures that all of the flip-flops receive the global reset signal within a same delayed clock cycle and that the flip-flops do not receive the global reset signal during a rising or falling edge of the clock signal.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: August 6, 2024
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Ankur Bal, Vikas Chelani
  • Patent number: 12054166
    Abstract: Methods and systems are provided for driveline control and diagnostics. In one example, a vehicle system may include a controller with instructions stored in a first memory unit and when executed by a first processing unit cause the controller to write mechanical vehicle component operating data to a shared memory unit. The controller further includes instructions stored in a second memory unit that when executed by a second processing unit cause the controller to read the mechanical vehicle component operating data to determine data validity.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: August 6, 2024
    Assignee: DANA BELGIUM N.V.
    Inventors: Peter Deckmyn, Bjorn Aelvoet
  • Patent number: D1038182
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: August 6, 2024
    Assignee: DAIKIN EUROPE N.V.
    Inventor: Hiroki Hayashi