Abstract: The present invention provides light-emitting diode (LED) devices comprises compositions and containers of hermetically sealed luminescent nanocrystals. The present invention also provides displays comprising the LED devices. Suitably, the LED devices are white light LED devices.
Type:
Application
Filed:
October 30, 2009
Publication date:
May 6, 2010
Applicant:
NANOSYS, Inc.
Inventors:
Robert S. DUBROW, Jian Chen, Veeral D. Hardev, Hans Jurgen Hofler, Ernest Lee
Abstract: The present invention is directed to a display using nanowire transistors. In particular, a liquid crystal display using nanowire pixel transistors, nanowire row transistors, nanowire column transistors and nanowire edge electronics is described. A nanowire pixel transistor is used to control the voltage applied across a pixel containing liquid crystals. A pair of nanowire row transistors is used to turn nanowire pixel transistors that are located along a row trace connected to the pair of nanowire row transistors on and off. Nanowire column transistors are used to apply a voltage across nanowire pixel transistors that are located along a column trace connected to a nanowire column transistor. Displays including organic light emitting diodes (OLED) displays, nanotube field effect displays, plasma displays, micromirror displays, micoelectromechanical (MEMs) displays, electrochromic displays and electrophoretic displays using nanowire transistors are also provided.
Abstract: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate.
Type:
Grant
Filed:
October 2, 2008
Date of Patent:
April 20, 2010
Assignee:
Nanosys, Inc.
Inventors:
Shahriar Mostarshed, Jian Chen, Francisco Leon, Yaoling Pan, Linda T. Romano
Abstract: Methods and systems for depositing nanomaterials onto a receiving substrate and optionally for depositing those materials in a desired orientation, that comprise providing nanomaterials on a transfer substrate and contacting the nanomaterials with an adherent material disposed upon a surface or portions of a surface of a receiving substrate. Orientation is optionally provided by moving the transfer and receiving substrates relative to each other during the transfer process.
Type:
Application
Filed:
August 21, 2006
Publication date:
March 25, 2010
Applicant:
Nanosys, Inc.
Inventors:
Robert Dubrow, Linda T. Romano, David Stumbo
Abstract: The present invention provides polymeric compositions that can be used to modify charge transport across a nanocrystal surface or within a nanocrystal-containing matrix, as well as methods for making and using the novel compositions.
Type:
Application
Filed:
July 2, 2009
Publication date:
March 18, 2010
Applicant:
NANOSYS, Inc.
Inventors:
Jeffery A. Whiteford, Mihai A. Buretea, Erik Scher, Linh Nguyen
Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrificial growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.
Abstract: A nanowire capacitor and methods of making the same are disclosed. The nanowire capacitor includes a subrate and a semiconductor nanowire that is supported by the substrate. An insulator is formed on a portion of the surface of the nanowire. Additionally, an outer coaxial conductor is formed on a portion insulator and a contact coupled to the nanowire.
Type:
Grant
Filed:
September 22, 2006
Date of Patent:
February 23, 2010
Assignee:
Nanosys, Inc.
Inventors:
David Stumbo, Jian Chen, David Heald, Yaoling Pan
Abstract: This invention provides compositions and devices having structurally ordered nanostructures, as well as methods for producing structurally ordered nanostructures.
Type:
Grant
Filed:
September 4, 2003
Date of Patent:
February 16, 2010
Assignee:
NANOSYS, Inc.
Inventors:
Jeffery A. Whiteford, Mihai Buretea, Erik Scher, Steve Empedocles, Andreas Meisel
Abstract: This invention provides novel nanofibers and nanofiber structures which posses adherent properties, as well as the use of such nanofibers and nanofiber comprising structures in the coupling and/or joining together of articles or material.
Abstract: Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and/or oriented nanostructures, devices that include populations of positioned and/or oriented nanostructures, systems for positioning and/or orienting nanostructures, and related devices, systems and methods.
Type:
Grant
Filed:
August 5, 2008
Date of Patent:
January 26, 2010
Assignee:
Nanosys, Inc.
Inventors:
Xiangfeng Duan, R. Hugh Daniels, Chunming Niu, Vijendra Sahi, James M. Hamilton, Linda T. Romano
Abstract: Matrixes doped with semiconductor nanocrystals are provided. In certain embodiments, the semiconductor nanocrystals have a size and composition such that they absorb or emit light at particular wavelengths. The nanocrystals can comprise ligands that allow for mixing with various matrix materials, including polymers, such that a minimal portion of light is scattered by the matrixes. The matrixes of the present invention can also be utilized in refractive index matching applications. In other embodiments, semiconductor nanocrystals are embedded within matrixes to form a nanocrystal density gradient, thereby creating an effective refractive index gradient. The matrixes of the present invention can also be used as filters and antireflective coatings on optical devices and as down-converting layers. Processes for producing matrixes comprising semiconductor nanocrystals are also provided.
Type:
Grant
Filed:
July 24, 2006
Date of Patent:
January 12, 2010
Assignee:
Nanosys, Inc.
Inventors:
J. Wallace Parce, Paul Bernatis, Robert Dubrow, William P. Freeman, Joel Gamoras, Shihai Kan, Andreas Meisel, Baixin Qian, Jeffery A. Whiteford, Jonathan Ziebarth
Abstract: Devices, compositions and methods for producing photoactive devices, systems and compositions that have improved conversion efficiencies relative to previously described devices, systems and compositions. This improved efficiency is generally obtained by one or both of improving the efficiency of light absorption into the photoactive component, and improving the efficiency of energy extraction from that active component.
Type:
Application
Filed:
June 11, 2009
Publication date:
January 7, 2010
Applicant:
NANOSYS, INC.
Inventors:
J. Wallace Parce, Calvin Y.H. Chow, Andreas P. Meisel, Linh Nguyen, Erik C. Scher, Jeffery A. Whiteford
Abstract: This invention provides composite materials comprising nanostructures (e.g., nanowires, branched nanowires, nanotetrapods, nanocrystals, and nanoparticles). Methods and compositions for making such nanocomposites are also provided, as are articles comprising such composites. Waveguides and light concentrators comprising nanostructures (not necessarily as part of a nanocomposite) are additional features of the invention.
Type:
Application
Filed:
September 4, 2009
Publication date:
December 24, 2009
Applicant:
NANOSYS, INC.
Inventors:
Mihai Buretea, Stephen Empedocles, Chunming Niu, Erik C. Scher
Abstract: A phased array system having antennas, non-variable phase shifters, and switches. The non-variable phase shifters are configured to be coupled selectively to a transmitter or a receiver. A non-variable phase shifter is configured to shift a phase of an electromagnetic energy wave that traverses the non-variable phase shifter by a fraction of a period of the electromagnetic energy wave for a range of frequencies of the electromagnetic energy wave. At least one of the fraction and the range associated with the non-variable phase shifter is different from at least one of the fraction and the range associated with other non-variable phase shifters. The switches are configured to couple selectively the antennas to the non-variable phase shifters, the transmitter, or the receiver.
Abstract: The present invention relates to treating of reflective surfaces to prevent fouling. The present invention also relates to reflective materials treated to prevent fouling, as well as methods of using such reflective materials.
Abstract: This invention provides composite materials comprising nanostructures (e.g., nanowires, branched nanowires, nanotetrapods, nanocrystals, and nanoparticles). Methods and compositions for making such nanocomposites are also provided, as are articles comprising such composites. Waveguides and light concentrators comprising nanostructures (not necessarily as part of a nanocomposite) are additional features of the invention.
Type:
Grant
Filed:
September 17, 2008
Date of Patent:
October 13, 2009
Assignee:
Nanosys, Inc
Inventors:
Mihai A. Bureatea, Stephen A. Empedocles, Chunming Niu, Erik C. Scher
Abstract: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device.
Type:
Grant
Filed:
December 21, 2004
Date of Patent:
September 29, 2009
Assignee:
Nanosys, Inc.
Inventors:
Xiangfeng Duan, Calvin Y. H. Chow, David L. Heald, Chunming Niu, J. Wallace Parce, David P. Stumbo
Abstract: The present invention relates to methods of forming substrate elements, including semiconductor elements such as nanowires, transistors and other structures, as well as the elements formed by such methods.
Type:
Application
Filed:
December 9, 2008
Publication date:
September 17, 2009
Applicant:
NANOSYS, Inc.
Inventors:
Francisco LEON, Francesco LEMMI, Jeffrey MILLER, David DUTTON, David P. STUMBO
Abstract: Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure and for reversibly modifying nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures.
Type:
Grant
Filed:
February 13, 2007
Date of Patent:
September 8, 2009
Assignee:
Nanosys, Inc.
Inventors:
Jeffery A. Whiteford, Mihai Buretea, William P. Freeman, Andreas Meisel, Kyu S. Min, J. Wallace Parce, Erik Scher
Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.