Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, two conductive features positioned apart from each other over the substrate, and a porous middle layer positioned between the two conductive features and adjacent to the two conductive features. A porosity of the porous middle layer is between about 25% and about 100%.

Abstract: The present application discloses a semiconductor device with an oxidized intervention layer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a tunneling insulating layer disposed over the substrate, a floating gate disposed over the tunnel oxide layer, a lateral oxidized intervention layer disposed over the floating gate, and a control gate disposed over the dielectric layer. The lateral oxidized intervention layer comprises a sidewall portion and a center portion, and the sidewall portion has a greater concentration of oxygen than the center portion.

Abstract: An electronic apparatus comprising a unified non-volatile memory and a control unit is disclosed. The unified non-volatile memory comprises a first memory section, served as a read only memory; and a second memory section, served as a random access memory. The control unit controls the unified non-volatile memory. The first memory section further comprises: a first area for the first memory section; and a second area for the first memory section. The control unit adjusts a refresh rate of the second memory section according to a number of access times of the second memory section.

Abstract: A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate.

Abstract: An access device includes a plurality of first digit lines (DL) trenches extending along a first direction, buried digit lines between each DL trench, second and third trenches separating the digit lines, a filling material filling the digit line trenches comprising airgaps in each second trench, a plurality of word line (WL) trenches extending along a second direction, metal word lines deposited on the walls of the word line trenches, a filling material filling the word line trenches.

Abstract: A power up detecting system for generating one of a first power up detecting signal and a second power up detecting signal as the final power up detecting signal, according to power provided by a power supplier. The power up detecting system comprises: a power up detecting module, controlled by a control signal to generate the first power up detecting signal in a first mode and to generate the second power up detecting signal in a second mode, wherein a voltage level of the first power up detecting signal is transited when the power reaches a first predetermined voltage value, and the voltage level of the second power up detecting signal is transited when the power reaches a second predetermined voltage value; where the first predetermined voltage value is higher than the second predetermined voltage value.

Abstract: A memory array structure includes: a plurality of array sections and a plurality of mini-gaps, wherein each mini-gap is disposed between two array sections of the plurality of array sections. Each mini-gap includes: a local write device, for providing a data signal in response to a write enable signal and a write data signal, the data signal for performing a write operation on a memory cell of an array section; and a local sensor, for outputting a data signal in response to an activation command and a read enable signal. The memory array further includes a control logic for providing the write enable and read enable signals, and at least one main sense amplifier, for providing the write data signal to the local write device, receiving the data signal from the local sensor, and amplifying the received data signal for providing a read data signal to output data lines.

Abstract: A method of manufacturing through silicon via stacked structures. A plurality of substrates is provided. At least one tapered hole is formed on one surface of each substrate. Each tapered hole is filled up with a tapered through silicon via. A recessed portion is formed on the wider end of each tapered through silicon via. A part of the substrate is removed until the narrower end of each tapered through silicon via protrudes from the other surface of the substrate. The substrates is stacked one after another by fitting and jointing the narrower end of each tapered through silicon via on one substrate into a corresponding recessed portion of the tapered through silicon via of another substrate.

Abstract: A method for forming a pattern includes steps of forming a patterned core layer on a substrate, conformally forming a spacer layer on the patterned core layer to form first concave portions, performing an etch back process to expose the patterned core layer, removing the exposed patterned core layer to form second concave portions, filling up the first concave portions and the second concave portions with a directed self-assembly material, and activating a directed self-assembly process, so that the directed self-assembly material is diffused to the perimeter of the concave portions to form a hole surrounding by the directed self-assembly material in each concave portions.

Abstract: A DRAM includes: a temperature sensor for monitoring a temperature operating condition of the DRAM; and a binary counter coupled to the temperature sensor, for receiving external commands to perform a refresh operation, and incrementing a count upon each received external command, wherein the refresh operation will be selectively skipped according to a value of the binary counter. The binary counter is activated to a first mode when the temperature sensor determines the temperature operating condition of the DRAM goes below a first threshold and activated to a second mode when the temperature sensor determines the temperature operating condition of the DRAM goes below a second threshold lower than the first threshold.

Abstract: A semiconductor device with neck fins comprises a substrate, a plurality of fins having a lower portion and a neck upper portion on the substrate, and insulators disposed between each fin and flush with the lower portion of the fins.

Abstract: A via chain testing structure includes: a substrate; a dielectric layer disposed on the substrate; a first via chain disposed on dielectric layer; a second via chain, being disposed on the dielectric on both sides of the first via chain and in thermal proximity with the first via chain; a first heating source disposed under the substrate, for providing thermal heat to the first via chain; and an electrical current source for heating the second via chain so the second via chain acts as a second heating source for the first via chain.

Abstract: A trench extends from a main surface of a semiconductor substrate to a predetermined depth. A gate oxide layer is formed in the trench. A buried gate electrode is formed at a lower portion of the trench. The buried gate electrode is capped with a dielectric layer. A pad layer and hard mask layer are formed on the semiconductor substrate. A recess through the pad layer and hard mask layer and into the semiconductor substrate is formed on one side of the trench. A portion of the dielectric layer is revealed within the recess. The hard mask layer is then removed. An ion implantation process is performed to implant dopants on both sides of the trench, thereby forming a source doping region and a drain doping region. The source doping region has a junction depth that is deeper than that of the drain doping region.

Abstract: A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.

Abstract: A through silicon via (TSV) stacked structure made of stacked substrates. Each substrate includes multiple tapered through silicon vias, wherein the wider end of each tapered through silicon via is provided with a recessed portion and the narrower end of each tapered through silicon via protrudes from the substrate. The substrates are stacked one after another with the narrower end of each tapered through silicon via being fitting and jointing into a corresponding recessed portion of the tapered through silicon via.

Abstract: A current conveyor circuit, which comprises: a first current transmitting route; a second current transmitting route, which has the same devices as the first current transmitting route; and at least one control circuit, to control the first current transmitting route and the second current transmitting route to enter a normal mode or a current splitting mode, wherein the first current transmitting route and the second current transmitting route are both enabled and can transmit current in the normal mode, where the first current transmitting route is enabled to transmit current but the second current transmitting route is disabled thus can not transmit current in the current splitting mode.

Abstract: A power up detecting system for generating one of a first power up detecting signal and a second power up detecting signal as the final power up detecting signal, according to power provided by a power supplier. The power up detecting system comprises: a power up detecting module, controlled by a control signal to generate the first power up detecting signal in a first mode and to generate the second power up detecting signal in a second mode, wherein a voltage level of the first power up detecting signal is transited when the power reaches a first predetermined voltage value, and the voltage level of the second power up detecting signal is transited when the power reaches a second predetermined voltage value; where the first predetermined voltage value is higher than the second predetermined voltage value.

Abstract: A capacitor includes a substrate, a multilayer over the substrate, a plurality of container-shaped storage node structures on the semiconductor substrate and surrounded by the multilayer, the storage node structure has a sidewall extending upwardly from the base to the top, where the sidewall includes an upper segment and a lower segment thinner than the upper segment, a capacitor dielectric material along a surface of each storage node structure, and a capacitor electrode material over the capacitor dielectric material.

Abstract: A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.

Abstract: A method for fabricating a capacitor includes: (1) forming a bottom electrode on a substrate; (2) forming a template layer on the bottom electrode; (3) performing a plurality of atomic layer deposition (ALD) cycles by using water vapor as an oxidant thereby depositing a first TiO2 layer on the template layer; and (4) performing ozone pulse and purge step to transform entire thickness of the first TiO2 layer into rutile phase.