Patents Assigned to Nanya Technology Corp.
  • Method of gate work function adjustment and metal gate transistor
    Patent number: 8614467
    Abstract: A method of gate work function adjustment includes the steps as follow. First, a substrate is provided, wherein a metal gate is disposed on the substrate, a source doping region and a drain doping region are disposed in the substrate at opposite sites of the metal gate, wherein the metal gate is divided into a source side adjacent to the source doping region, and a drain side adjacent to the drain doping region. Later, a mask layer is formed to cover the source doping region and the drain doping region. After that, an implantation process is performed to implant nitrogen into the metal gate so as to make a first nitrogen concentration of the source side higher than a second nitrogen concentration of the drain side. Finally, the mask layer is removed.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: December 24, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Slit Recess Channel Gate
    Publication number: 20130307067
    Abstract: A slit recess channel gate is provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer.
    Type: Application
    Filed: August 5, 2013
    Publication date: November 21, 2013
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Voltage generator having pull-up circuit and pull-down circuit
    Patent number: 8587273
    Abstract: A voltage generator includes a controllable voltage divider, a pull-up circuit and a first pull-down circuit. The controllable voltage divider is utilized for generating an output voltage at an output node of the controllable voltage divider according to a first reference voltage, a second reference voltage, and a control signal, wherein the second reference voltage is lower than the first reference voltage. The pull-up circuit is coupled to the output node of the controllable voltage divider and the first reference voltage, and is utilized for selectively connecting the first reference voltage to the output node of the controllable voltage divider. The first pull-down circuit is coupled to the output node of the controllable voltage divider and the second reference voltage, and is utilized for selectively connecting the second reference voltage to the output node of the controllable voltage divider.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: November 19, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Chih-Jen Chen, Kuang-Wei Chao
  • Through-silicon via and fabrication method thereof
    Patent number: 8587131
    Abstract: A through silicon via (TSV) structure including a semiconductor substrate; a first inter-metal dielectric (IMD) layer on the semiconductor substrate; a cap layer overlying the IMD layer; a conductive layer extending through the cap layer, the first IMD layer and into the semiconductor substrate; a tungsten film capping a top surface of the conductive layer; a second IMD layer overlying the cap layer and covering the tungsten film; and an interconnect feature in the second IMD layer.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: November 19, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Chi-Wen Huang, Kuo-Hui Su
  • Capacitor formation for a pumping circuit
    Patent number: 8587047
    Abstract: A capacitor structure for a pumping circuit includes a substrate, a U-shaped bottom electrode in the substrate, a T-shaped top electrode in the substrate and a dielectric layer disposed between the U-shaped bottom and T-shaped top electrode. The contact area of the capacitor structure between the U-shaped bottom and T-shaped top electrode is extended by means of the cubic engagement of the U-shaped bottom electrode and the T-shaped top electrode.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: November 19, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Yu-Wei Ting, Shing-Hwa Renn, Yu-Teh Chiang, Chung-Ren Li, Tieh-Chiang Wu
  • Voltage pumping circuit
    Patent number: 8587367
    Abstract: A voltage pumping circuit for pumping an input voltage to generate an output voltage, which comprises: a first voltage pumping path including a first number of pumping stages; and a second voltage pumping path including a second number of pumping stages, wherein the second number is less than the first number. Only one of the first voltage pumping path and the second voltage pumping path is activated according to at least one path selecting signal to pump the input voltage to generate the output voltage.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: November 19, 2013
    Assignee: Nanya Technology Corp.
    Inventor: Dong Pan
  • Process of planarizing a wafer with a large step height and/or surface area features
    Patent number: 8580690
    Abstract: A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: November 12, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Brett Busch, Gowri Damarla, Anurag Jindal, Chia-Yen Ho, Thy Tran
  • Local IO sense accelerator for increasing read/write data transfer speed
    Patent number: 8553480
    Abstract: A memory array includes: at least one differential local bit line pair; at least one differential global bit line pair; at least a column selection signal, for charging the differential local bit line pair to a predetermined voltage; at least an enable signal for coupling the differential local bit line pair to the differential global bit line pair when a voltage of the differential local bit line pair reaches a specific value; and a local sense accelerator, coupled to the differential local bit line pair, for determining a voltage of the differential local bit line pair, and enabling an accelerator signal for latching one of the differential local bit line pair and pulling the other low when the voltage reaches the specific value.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: October 8, 2013
    Assignee: Nanya Technology Corp.
    Inventor: One-Gyun Na
  • Chip stack package having spiral interconnection strands
    Patent number: 8546946
    Abstract: A chip stack package is provided. The chip stack package includes an n number of chips stacked on each other and an n number of interconnection strands connecting the chips. The interconnection strands are spirally rotated and insulated from each other. In one embodiment, the chips are substantially structurally identical. In another embodiment, each of the interconnection strands is electrically coupled to a chip selection signal.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: October 1, 2013
    Assignee: Nanya Technology Corp.
    Inventor: Shu-Liang Nin
  • MAGNETORESISTIVE RANDOM ACCESS MEMORY ELEMENT AND FABRICATION METHOD THEREOF
    Publication number: 20130252348
    Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.
    Type: Application
    Filed: May 27, 2013
    Publication date: September 26, 2013
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: Chun-I Hsieh, Chang-Rong Wu
  • Semiconductor structure and fabrication method thereof
    Patent number: 8536635
    Abstract: A semiconductor structure includes a semiconductor substrate having thereon a plurality of deep trenches and a plurality of pillar structures between the deep trenches, wherein each of the plurality of pillar structures comprises an upper portion and a lower portion. A doping region is formed in the lower portion. A diffusion barrier layer is disposed on a sidewall of the lower portion.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: September 17, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Chien-An Yu, Yuan-Sung Chang, Feng-Ling Chen, Chun-Hung Chien
  • Photomask and method for forming overlay mark using the same
    Patent number: 8535858
    Abstract: The present invention relates to a photomask and a method for forming an overlay mark in a substrate using the same. The photomask comprises a plurality of patterns. At least one of the patterns comprises a plurality of ring areas and a plurality of inner areas enclosed by the ring areas, wherein the light transmittancy of the ring areas is different from that of the inner areas. When the photomask is applied in a photolithography process, the formed overlay mark has a large thickness. Therefore, the contrast is high when a metrology process is performed, and it is easy to find the overlay mark.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: September 17, 2013
    Assignee: Nanya Technology Corp.
    Inventor: Chui Fu Chiu
  • Magnetoresistive random access memory element and fabrication method thereof
    Patent number: 8535954
    Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: September 17, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Chun-I Hsieh, Chang-Rong Wu
  • Method of forming a slit recess channel gate
    Patent number: 8530306
    Abstract: A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: September 10, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Transistor with buried fins
    Patent number: 8525262
    Abstract: The present invention disclosed a recessed gate transistor with buried fins. The recessed gate transistor with buried fins is disposed in an active region on a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate, and sandwich the active region. A gate structure is disposed in the semiconductor substrate, wherein the gate structure includes: an upper part and a lower part. The upper part is disposed in the active region and a lower part having a front fin disposed in one of the two isolation regions, at least one middle fin disposed in the active region, and a last fin disposed in the other one of the two isolation regions, wherein the front fin are both elliptic cylindrical.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: September 3, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Method for forming a deep trench
    Patent number: 8524093
    Abstract: A method for forming a deep trench includes providing a substrate with a bottom layer and a top layer; performing a first etching process to etch the top layer, the bottom layer and the substrate so as to form a recess; selectively depositing a liner covering the top layer, the bottom layer and part of the substrate in the recess; using the liner as an etching mask to perform a second dry etching to etch the recess unmasked by the liner so as to form a deep trench; performing a selective wet etching to remove the top layer; and performing a post wet etching to enlarge the deep trench.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: September 3, 2013
    Assignee: Nanya Technology Corp.
    Inventor: Chung-Chiang Min
  • Memory cell and memory array utilizing the memory cell
    Patent number: 8520427
    Abstract: A memory cell comprising a first switch device, a second switch device and a capacitor is disclosed. The first switch device has: a control terminal coupled to a select line, wherein the first switch device is controlled by the select line; a first terminal, coupled to a bit line parallel with the select line. The second switch device has: a first terminal, coupled to the second terminal of the first switch device; a control terminal, coupled to a word line orthogonal to the bit line and the select line, wherein the second switch device is controlled by the word line. The capacitor has a first terminal coupled to the second terminal of the second switch device and a second terminal coupled to a predetermined voltage level, wherein the data is read from the capacitor or written to the capacitor via the bit line.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: August 27, 2013
    Assignee: Nanya Technology Corp.
    Inventor: Tah-Kang Joseph Ting
  • Test mode initialization device and method
    Patent number: 8514643
    Abstract: A die includes: a plurality of efuses, for respectively generating a plurality of test-mode signals; a control unit, coupled to a first control signal, for generating a plurality of control bits; a multiplexer, coupled to the plurality of test-mode signals and the control unit, for muxing the plurality of test-mode signals in series in response to the plurality of control bits; at least an address block, for receiving a specific test-mode signal; and at least a local test-mode block coupled to the address block. The local test-mode block comprises: a latch, for latching a specific test-mode signal and releasing the latched test-mode signal to the address block in response to a second control signal; a first decoder, for releasing the specific test-mode signal to the latch in response to the plurality of control bits; and a second decoder, for generating the second control signal to the latch.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 20, 2013
    Assignee: Nanya Technology Corp.
    Inventor: Hermann Wienchol
  • Method for fabricating a recessed channel access transistor device
    Patent number: 8501566
    Abstract: A method for fabricating a recessed channel access transistor device is provided. A semiconductor substrate having thereon a recess is provided. A gate dielectric layer is formed in the recess. A gate material layer is then deposited into the recess. A dielectric cap layer is formed on the gate material layer. The dielectric cap layer and the gate material layer are etched to form a gate pattern. A liner layer is then formed on the gate pattern. A spacer is formed on the liner layer on each sidewall of the gate pattern. The liner layer not masked by the spacer is etched to form an undercut recess that exposes a portion of the gate material layer. The spacer is then removed. The exposed portion of the gate material layer in the undercut recess is oxidized to form an insulation block therein.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: August 6, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Chung-Yen Chou, Tieh-Chiang Wu, Hsin-Jung Ho
  • Multi-level DRAM cell using CHC technology
    Patent number: 8497550
    Abstract: A DRAM memory cell includes: a first finFET structure; and a second finFET structure adjacent to the first finFET structure. The second finFET structure includes: a source follower transistor in a first fin of the second finFET structure; an access transistor in a second fin of the second fin FET structure; a write word line; and a read word line stacked above the write word line. When the read word line is fired high, the source follower transistor enables data to be read from the first finFET structure.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: July 30, 2013
    Assignee: Nanya Technology Corp.
    Inventor: Werner Juengling