Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate having a trench. The method also includes forming a first buffer layer in the trench. The method further includes forming a doped-polysilicon layer on the first buffer layer in the trench. The method also includes performing a thermal treatment on the doped-polysilicon layer.

Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a substrate including a plurality of active areas separated from each other. In some embodiments, the method also includes forming first mask structures on the substrate. In some embodiments, the method further includes forming a first protective layer covering the first mask structures and the substrate. In some embodiments, the first protective layer defines an area exposing a portion of the first mask structures and the substrate, and the area defined by the first protective layer has a zigzag edge in a top view. In addition, the method includes performing a first etching process to remove a portion of the substrate exposed from the first mask structures and the first protective layer to form trenches.

Abstract: A method for manufacturing a semiconductor device structure includes forming a first metallization line and a second metallization line extending along a first direction; forming a first isolation feature and a second isolation feature between the first metallization line and the second metallization line, wherein the first metallization line, the second metallization line, the first isolation feature and the second isolation feature define an aperture; forming a profile modifier within the aperture, wherein the profile modifier comprises a plurality of segments spaced apart from each other, wherein each of the segments are located at corners of the aperture; and forming a contact feature surrounded by the plurality of segments.

Abstract: A method for preparing a semiconductor device structure includes forming a first fin structure and a second fin structure over a semiconductor substrate, forming an isolation structure over the semiconductor substrate, partially removing the first fin structure and the second fin structure to form a recessed portion of the first fin structure and a recessed portion of the second fin structure, epitaxially growing a first source/drain (S/D) structure over the recessed portion of the first fin structure and a second S/D structure over the recessed portion of the second fin structure, partially removing the isolation structure through the first opening to form a second opening, and forming a contact etch stop layer (CESL) over the first S/D structure and the second S/D structure such that an air gap is formed and sealed in the first opening and the second opening.

Abstract: An electronic device and a method of controlling an electronic device are provided. The electronic device includes a first transistor having a first resistor, second resistor, first transistor, and second transistor. The second resistor is connected to the first resistor. The first transistor is connected to the first resistor in parallel and has a first bulk. The second transistor is connected to the second resistor in parallel and has a second bulk. The first bulk of the first transistor receives a first voltage and the first bulk of the second transistor receives a second voltage. The first voltage and the second voltage are different.

Abstract: The present disclosure provides a mothed of method of manufacturing a semiconductor device. The method includes steps of forming a dielectric layer on a substrate; etching the dielectric layer to create a plurality of openings in the dielectric layer; applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer; forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed; removing the sacrificial layer to form at least one air gap in the dielectric layer; and forming a plurality of protrusions on the bases.

Abstract: The present application discloses provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a sacrificial structure above the substrate, forming a supporting liner covering the sacrificial structure, forming an energy-removable layer covering the supporting liner, performing a planarization process until a top surface of the sacrificial structure is exposed, performing an etch process to remove the sacrificial structure and concurrently form a first opening in the energy-removable layer, forming covering liners on sidewalls of the first opening and on a top surface of the energy-removable layer, forming a first conductive feature in the first opening, and applying an energy source to turn the energy-removable layer into a porous insulating layer.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device having a buried wordline. The method includes forming a first recessed portion in a first dielectric layer in a substrate; forming a second recessed portion spaced apart from the first recessed portion and in the substrate; disposing a protection layer on the substrate to cover the second recessed portion; and disposing a second dielectric layer on the first dielectric layer.

Abstract: The present disclosure relates to a semiconductor device with an air gap below a landing pad and a method for forming the semiconductor device. The semiconductor device includes a first lower plug and a second lower plug disposed over a semiconductor substrate. The semiconductor device also includes a first landing pad disposed over a top surface and upper sidewalls of the first lower plug, and a first upper plug disposed over the first landing pad and electrically connected to the first lower plug. A width of the first lower plug is greater than a width of the first upper plug. The semiconductor device further includes a dielectric layer disposed over the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad and the first upper plug are disposed in the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.

Abstract: A method of operating a testing system comprising a plurality of testing slots. The method comprising: testing the testing slots; obtaining a current testing data from the testing slots; determining whether one of the testing slots is abnormal by comparing the current testing data with a former testing data; shutting down the one of the testing slots and sending a repairing notification if the one of the testing slots is determined to be abnormal; performing a confirmation procedure to determine whether the one of the testing slots is repaired to be normal; and restarting the one of the testing slots if the one of the testing slots passes the confirmation procedure.

Abstract: An electrical over stress protection device is provided. A detection circuit detects an input voltage from a pad, provides a first discharge path when the input voltage is higher than a preset voltage, and provides a turn-on voltage to a discharge protection circuit to control the discharge protection circuit to provide at least one second discharge path.

Abstract: A method for fabricating the semiconductor device includes providing a substrate, forming a bottom conductive plug on the substrate, forming a semiconductor layer on the bottom conductive plug, rounding a top surface of the semiconductor layer, turning the semiconductor layer into an intervening conductive layer, and forming a top conductive plug on the intervening conductive layer

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a surface. The surface has a first portion and a second portion protruding from the first portion. The semiconductor device also includes a dielectric layer disposed on the second portion and a gate conductive layer disposed on the dielectric layer.

Abstract: The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Abstract: The present application provides a method of manufacturing a memory device having a word line (WL) with improved adhesion between a work function member and a conductive layer. The method includes steps of providing a semiconductor substrate defined with an active area and including an isolation structure surrounding the active area; forming a recess extending into the semiconductor substrate and across the active area; forming a first insulating layer conformal to the recess; disposing a first conductive material conformal to the first insulating layer; forming a conductive member surrounded by the first conductive material; disposing a second conductive material over the conductive member and removing a portion of the first conductive material above the second conductive material to form a conductive layer enclosing the conductive member; and forming a second insulating layer over the conductive layer and conformal to the first insulating layer.

Abstract: The present disclosure provides a semiconductor structure having a bit line with a tapered configuration. The semiconductor structure includes: a substrate; a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion; a polysilicon layer, disposed over the substrate and around the bit line structure; and a landing pad, disposed over the polysilicon layer and the step portion.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.

Abstract: The present disclosure provides a semiconductor device with an interconnect part and a method for preparing the semiconductor device. The semiconductor device comprises a device substrate and an interconnect part disposed over the device substrate. The interconnect part includes a lower redistribution layer electrically connected to the backside contact, and an upper redistribution layer disposed over the lower redistribution layer. The interconnect part also includes an interconnect frame disposed between and electrically connected to the lower redistribution layer and the upper redistribution layer. The interconnect part further includes a passivation structure surrounding the interconnect frame.

Abstract: The present disclosure provides a method for preparing a semiconductor device. The method includes forming a sacrificial source/drain structure over a first carrier substrate; forming a redistribution structure over the sacrificial source/drain structure; attaching the redistribution structure to a second carrier substrate; removing the first carrier substrate after the redistribution structure is attached to the second carrier substrate; replacing the sacrificial source/drain structure with a first source/drain structure; forming a backside contact over and electrically connected to the first source/drain structure; and forming an interconnect part over the backside contact.