Abstract: A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant.

Abstract: In a system and method to reduce wafer breakages in a wafer handling system, the position of a wafer on a platen is monitored and closing of the platen on a vacuum chamber is prevented if a misaligned wafer is detected. In one embodiment the wafer position is monitored by monitoring the air pressure in vacuum channels of a platen faceplate.

Abstract: In an ESD protection device making use of a LVTSCR, at least one contacted drain and at least one emitter are formed, and are arranged laterally next to each other to be substantially equidistant from the gate of the LVTSCR, to improve holding voltage and decrease size. The ratio of emitter width to contacted drain width is adjusted to achieve the desired characteristics.

Abstract: In a circuit and method for adjusting rise-and-fall-time changes in an output driver signal due to changes in temperature, process or voltage, the driver output voltage is monitored and current flow through a constant load resistor adjusted as the voltage changes. The current may be adjusted by controlling the gate-source voltage on a transistor. The gate voltage on the transistor may also be used to adjust the power supply to pre-drivers of the output driver.

Abstract: In a semiconductor structure, interconnects between regions of a single device or different devices are achieved by forming contacts or plugs in thick oxide holes that span across the regions to be interconnected.

Abstract: In a high tolerance I/O interface with over-voltage protection during 5V tolerant mode and back-drive mode, includes pass gate circuitry to isolate the output of the driver circuit and input of the receiver circuit from the pad voltage during stress mode. The gate voltage of the PMOS transistor of the pass gate is charged up to avoid gate oxide breakdown during stress mode. Also, the gate and well of the driver pull-up transistor are charged to NG1 to avoid current flow through the transistor and to its well.

Abstract: A circuit with low noise and reduced offset that feeds an input of an opamp with a programmable feedback resistor that provides variable gain settings. Input biasing currents are varied using control bits that are also used to adjust the gain. When the input signal is small (gain at higher setting), a minimum bias current is provided to source the input voltage swing. This scheme reduces the noise and offset generated by the lower transconductance of a biasing transistor while maintaining a constant SNR and fixed offset even in the presence of relatively small input swings. Also, when the input signal is large (gain at lower setting), a maximum bias current can be provided to accommodate the relatively large input swing level. Although the overall noise and offset current are increased for large input swings, the overall SNR and offset is maintained for relatively lower input swings.

Abstract: The present invention is directed to a photogate based pixel cell with an electronic shutter and which provides relatively low lag and high sensitivity for sensing infrared light reflected from objects. Additionally, this invention eliminates the need for a transfer gate in the pixel cell. In one embodiment, the reset and shutter transistors are implemented with PMOS transistors so that the pixel cell can have an increased dynamic range and a relatively high voltage swing. In another embodiment, the actual size of each pixel cell can be further reduced when the reset gate and the electronic shutter are implemented with NMOS transistors. Also, when a P− well is not disposed beneath the photogate, the ability of the pixel cell to sense infrared light is improved. Correlated double sampling can be used to improve the accuracy of the signal read out from the pixel cell.

Abstract: In a high speed BJT device, the method for producing the device includes forming a self-aligned BJT through the use of a single mask by making use of a single layer of polysilicon. The method includes forming a window in the polysilicon to define a base poly region and an emitter poly region. An underlying oxide/nitride stack is etched in a two etch process to define base and emitter regions for growing a small base and a small emitter. This displays small base-collector and base-emitter junction regions to reduce the capacitance.

Abstract: In an ESD protection circuit for an analog bipolar circuit, the avalanche breakdown voltage of a BJT acting as an avalanche diode is reduced by injecting current into the base of the BJT. This is achieved through the use of a capacitor connected between Vdd and the base of the avalanche BJT to speed up the switching of the protection circuit.

Abstract: In a stand-alone snapback NMOS ESD protection structure method of manufacturing, the breakdown voltage is reduced and the structure is made more resilient to hot carrier and soft leakage degradation in the gate region by blocking the NLDD and partially blocking the n+ drain region between the gate and drain region.

Abstract: The present invention relates to a method for over-current protection of an amplifier circuit, which comprises driving an electronic load with the output of the amplifier circuit and sensing for a fault condition in the load, such as a short or over-current condition. The amplifier is switched off in response to the fault condition and can stay off for a specified time delay and the amplifier is then switched on. The fault condition is tested for again and, if cured, the amplifier can remain on until a new fault condition is detected. If the fault condition remains, testing and switching the amplifier on and off over very short time periods results in an effectively limited current in the load.

Abstract: In a ESD protection clamp, breakdown and triggering voltage of the structure are reduced by introducing an internal zener diode structure that has a lower avalanche breakdown than the p-n junction of the ESD device. This introduces extra holes into the source junction region causing electrons to be injected into the junction and into the drain junction region to increase the carrier multiplication rate to increase the current density and lower the triggering voltage and breakdown voltage of devices such as NMOS devices or LVTSCRs.

Abstract: In a capacitive structure of an integrated circuit a comb-like configuration or other thin element configuration provides for capacitive coupling between electrode elements in one plane. By forming electrodes in a plurality of planes and selectively shifting the positioning of the electrodes in one plane relative to those in another plane, capacitive coupling between the electrodes in the different planes is achieved. In this way capacitance and stability with process variations can be affected. Furthermore, by using the metal interconnect layers to form the capacitive structures, the need for additional process steps in defining poly-layers, is avoided.

Abstract: An electronic circuit generates a bias current that is proportional to a frequency of a reference clock signal in a switched capacitor circuit. The electronic circuit includes a capacitive circuit selectively coupled to a transistor supplied by a voltage reference circuit. During a first phase the capacitive circuit is charged by a current from the transistor, and during the second phase the capacitive circuit is discharged to ground. The duration of each phase is related to the reference clock signal. The average current corresponds to a bias signal and is filtered to reduce ripple in the bias signal before the bias signal is received by the switched capacitor circuit. The capacitive circuit is configured with a first and second capacitor arranged in a complimentary out-of-phase configuration. During a first phase, the first capacitor is charged and the second capacitor is discharged. During the second phase, the second capacitor is charged and the first capacitor is discharged.

Abstract: A high-Q spiral inductor structure that utilizes a three-layer substrate, and methods of manufacturing the structure, are provided. The three-layer substrate is utilizable for CMOS circuits while at the same time minimizing eddy current induction and increasing the inductor quality factor Q of the structure.

Abstract: An output buffer circuit includes multiple programmable boost drive stages which allow selection of one of several drive strengths to accommodate a range of output load conditions, thereby achieving low noise and low power dissipation. In one embodiment, one or more of the boost circuits turn on after the primary driver circuit is turned on, and turn off before the primary circuit is turned off, thereby achieving soft turn-on and turn-off.

Abstract: A light shield is provided for light sensitive flip chip integrated circuits. The flip chip includes an under bump layer to portions of which solder bumps are attached. A separate portion of this under bump layer is used to provide the light shield. The light shield excludes ambient light from the most light sensitive portions of the circuit so that the electrical characteristics of the flip chip integrated circuit are not significantly altered when the flip chip is operated in ambient light.

Abstract: Acid diffusion induced critical dimension change in a chemically amplified photoresist process is suppressed by lowering the reaction activation energy barrier. Energy required to overcome the reaction activation energy barrier is provided directly to the chemical bonds that are involved in the chemical reactions, rather than providing energy solely by thermal heating, thereby significantly increasing reaction rate without increasing acid diffusion.

Abstract: A thermal coupler utilizes Peltier heating and cooling to transmit a thermal signal across an electrical isolation barrier. Application of a potential difference across a thermal emitter in the form of a first pair of parallel strips of electrically conducting materials separated by a second electrically conducting material results in a temperature difference arising at junctions between the first electrically conducting material and the second electrically conducting material. This temperature difference is propagated across the electrical isolation barrier to a similar thermal detector structure lacking an applied voltage and possessing a second pair of junctions. Differential heating of the second pair of junctions of the thermal detector creates a Seebeck voltage in the thermal detector. This Seebeck voltage is amplified and processed as a communication signal.