Patents Assigned to National Semiconductor Corp.
  • Patent number: 8086979
    Abstract: A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: December 27, 2011
    Assignee: National Semiconductor Corp.
    Inventors: Douglas Brisbin, Andrew Strachan
  • Patent number: 7714355
    Abstract: In a BSCR or BJT ESD clamp, the breakdown voltage and DC voltage tolerance are controlled by controlling the size of the collector of the BJT device by masking part of the collector.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: May 11, 2010
    Assignee: National Semiconductor Corp
    Inventors: Vladislav Vashchenko, Alexei Sadovnikov, Peter J. Hopper, Andy Strachan
  • Patent number: 6934595
    Abstract: In a system and method to reduce wafer breakages in a wafer handling system, the position of a wafer on a platen is monitored and closing of the platen on a vacuum chamber is prevented if a misaligned wafer is detected. In one embodiment the wafer position is monitored by monitoring the air pressure in vacuum channels of a platen faceplate.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: August 23, 2005
    Assignee: National Semiconductor Corp.
    Inventor: Allan Daniel O'Brien
  • Patent number: 6911679
    Abstract: In an ESD protection device making use of a LVTSCR, at least one contacted drain and at least one emitter are formed, and are arranged laterally next to each other to be substantially equidistant from the gate of the LVTSCR, to improve holding voltage and decrease size. The ratio of emitter width to contacted drain width is adjusted to achieve the desired characteristics.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: June 28, 2005
    Assignee: National Semiconductor Corp.
    Inventors: Vladislav Vashchenko, Ann Concannon, Marcel ter Beek, Peter J. Hopper
  • Patent number: 6894881
    Abstract: In an ESD protection circuit, diodes for shunting current through an ESD clamp include a third terminal in order to provide a dual current path through the diode structure and provide for a voltage drop to the input of the protected internal circuit. In another embodiment, where a bipolar junction transistor is used as an ESD clamp to shunt current to ground between an I/O pad and an input to a protected internal circuit, a lower voltage is provided to the internal circuit by providing a voltage drop across an internal resistive element of the bipolar junction transistor. This is achieved by making use of two base terminals, one connected to the I/O pad, and the other connected to the input of the internal circuit and spaced from the first contact by the base polysilicon region of the bipolar junction transistor.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: May 17, 2005
    Assignee: National Semiconductor Corp
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper
  • Patent number: 6888388
    Abstract: In a circuit and method for adjusting rise-and-fall-time changes in an output driver signal due to changes in temperature, process or voltage, the driver output voltage is monitored and current flow through a constant load resistor adjusted as the voltage changes. The current may be adjusted by controlling the gate-source voltage on a transistor. The gate voltage on the transistor may also be used to adjust the power supply to pre-drivers of the output driver.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: May 3, 2005
    Assignee: National Semiconductor Corp.
    Inventors: Richard W. Cook, Steven M. Macaluso
  • Patent number: 6864582
    Abstract: In a semiconductor structure, interconnects between regions of a single device or different devices are achieved by forming contacts or plugs in thick oxide holes that span across the regions to be interconnected.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: March 8, 2005
    Assignee: National Semiconductor Corp.
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Philipp Lindorfer, Andy Strachan, Peter Johnson
  • Patent number: 6809574
    Abstract: In a high tolerance I/O interface with over-voltage protection during 5V tolerant mode and back-drive mode, includes pass gate circuitry to isolate the output of the driver circuit and input of the receiver circuit from the pad voltage during stress mode. The gate voltage of the PMOS transistor of the pass gate is charged up to avoid gate oxide breakdown during stress mode. Also, the gate and well of the driver pull-up transistor are charged to NG1 to avoid current flow through the transistor and to its well.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: October 26, 2004
    Assignee: National Semiconductor Corp.
    Inventor: Khusrow Kiani
  • Patent number: 6724251
    Abstract: A circuit with low noise and reduced offset that feeds an input of an opamp with a programmable feedback resistor that provides variable gain settings. Input biasing currents are varied using control bits that are also used to adjust the gain. When the input signal is small (gain at higher setting), a minimum bias current is provided to source the input voltage swing. This scheme reduces the noise and offset generated by the lower transconductance of a biasing transistor while maintaining a constant SNR and fixed offset even in the presence of relatively small input swings. Also, when the input signal is large (gain at lower setting), a maximum bias current can be provided to accommodate the relatively large input swing level. Although the overall noise and offset current are increased for large input swings, the overall SNR and offset is maintained for relatively lower input swings.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: April 20, 2004
    Assignee: National Semiconductor Corp.
    Inventors: Ramsin M. Ziazadeh, Jitendra Mohan, Abu-Hena Mostafa Kamal
  • Patent number: 6720592
    Abstract: The present invention is directed to a photogate based pixel cell with an electronic shutter and which provides relatively low lag and high sensitivity for sensing infrared light reflected from objects. Additionally, this invention eliminates the need for a transfer gate in the pixel cell. In one embodiment, the reset and shutter transistors are implemented with PMOS transistors so that the pixel cell can have an increased dynamic range and a relatively high voltage swing. In another embodiment, the actual size of each pixel cell can be further reduced when the reset gate and the electronic shutter are implemented with NMOS transistors. Also, when a P− well is not disposed beneath the photogate, the ability of the pixel cell to sense infrared light is improved. Correlated double sampling can be used to improve the accuracy of the signal read out from the pixel cell.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: April 13, 2004
    Assignee: National Semiconductor Corp.
    Inventors: Willem Johannes Kindt, Philipp Lindorfer
  • Patent number: 6710622
    Abstract: In a one-shot, the pulse duration is adjustable through the use of a counter and one or more programmable delay lines in one or more of the feedback loops of the one-shot. The one-shot makes use of at least two flip-flops, and the output of the counter resets the flip-flops.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: March 23, 2004
    Assignee: National Semiconductor Corp
    Inventor: Wai Cheong Chan
  • Patent number: 6696342
    Abstract: In a high speed BJT device, the method for producing the device includes forming a self-aligned BJT through the use of a single mask by making use of a single layer of polysilicon. The method includes forming a window in the polysilicon to define a base poly region and an emitter poly region. An underlying oxide/nitride stack is etched in a two etch process to define base and emitter regions for growing a small base and a small emitter. This displays small base-collector and base-emitter junction regions to reduce the capacitance.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: February 24, 2004
    Assignee: National Semiconductor Corp.
    Inventors: Mohamed N. Darwish, Alexei Sadovinkov, Reda Razouk
  • Patent number: 6690069
    Abstract: In an ESD protection device using a SCR-like structure, a vertical device is provided that is highly robust and easily allows the triggering voltage to be adjusted during manufacture. Furthermore it is implementable in complementary form based on PNP and NPN BJT structures, to provide both positive and negative pulse protection.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: February 10, 2004
    Assignee: National Semiconductor Corp
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek
  • Patent number: 6667867
    Abstract: In an ESD protection circuit for an analog bipolar circuit, the avalanche breakdown voltage of a BJT acting as an avalanche diode is reduced by injecting current into the base of the BJT. This is achieved through the use of a capacitor connected between Vdd and the base of the avalanche BJT to speed up the switching of the protection circuit.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: December 23, 2003
    Assignee: National Semiconductor Corp.
    Inventors: Vladislav Vashchenko, Peter J. Hopper
  • Patent number: 6660602
    Abstract: In a stand-alone snapback NMOS ESD protection structure method of manufacturing, the breakdown voltage is reduced and the structure is made more resilient to hot carrier and soft leakage degradation in the gate region by blocking the NLDD and partially blocking the n+ drain region between the gate and drain region.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: December 9, 2003
    Assignee: National Semiconductor Corp.
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek
  • Patent number: 6621336
    Abstract: The present invention relates to a method for over-current protection of an amplifier circuit, which comprises driving an electronic load with the output of the amplifier circuit and sensing for a fault condition in the load, such as a short or over-current condition. The amplifier is switched off in response to the fault condition and can stay off for a specified time delay and the amplifier is then switched on. The fault condition is tested for again and, if cured, the amplifier can remain on until a new fault condition is detected. If the fault condition remains, testing and switching the amplifier on and off over very short time periods results in an effectively limited current in the load.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: September 16, 2003
    Assignee: National Semiconductor Corp.
    Inventor: Nick M. Johnson
  • Patent number: 6548868
    Abstract: In a ESD protection clamp, breakdown and triggering voltage of the structure are reduced by introducing an internal zener diode structure that has a lower avalanche breakdown than the p-n junction of the ESD device. This introduces extra holes into the source junction region causing electrons to be injected into the junction and into the drain junction region to increase the carrier multiplication rate to increase the current density and lower the triggering voltage and breakdown voltage of devices such as NMOS devices or LVTSCRs.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: April 15, 2003
    Assignee: National Semiconductor Corp.
    Inventors: David Tsuei, Vladislav Vashchenko
  • Patent number: 6542351
    Abstract: In a capacitive structure of an integrated circuit a comb-like configuration or other thin element configuration provides for capacitive coupling between electrode elements in one plane. By forming electrodes in a plurality of planes and selectively shifting the positioning of the electrodes in one plane relative to those in another plane, capacitive coupling between the electrodes in the different planes is achieved. In this way capacitance and stability with process variations can be affected. Furthermore, by using the metal interconnect layers to form the capacitive structures, the need for additional process steps in defining poly-layers, is avoided.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: April 1, 2003
    Assignee: National Semiconductor Corp.
    Inventor: Kyuwoon Kwang
  • Patent number: 6452414
    Abstract: A power-on sense circuit accurately senses a power-on condition when a power supply voltage exceeds a desired trigger voltage level. The power-on sense circuit includes a voltage-to-current converter circuit and a beta-multiplier reference circuit. The voltage-to-current converter circuit and the beta-multiplier reference circuit generate currents that relate to the power supply voltage. By sensing a balanced current operating condition with the beta-multiplier reference circuit, the power-on sense circuit determines when a desired trigger voltage has been achieved. The trigger voltage level has a zero temperature coefficient at median operating temperatures, and has a slightly downward curvature shape without the need for high-current resistor-dividers or bandgap circuits. The power-on sense circuit may be adapted for use as a power-on reset signal. By adding an amplifier stage to the outputs signal, the power-on sense circuit may also be used as an analog reference voltage generator.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: September 17, 2002
    Assignee: National Semiconductor Corp. Inc.
    Inventor: Perry Scott Lorenz
  • Patent number: 6452255
    Abstract: A variety of leadless packaging arrangements and methods of packaging integrated circuits in leadless packages that are arranged to have relatively low inductance are disclosed. In one aspect, a leadless semiconductor package is described having an exposed die pad and a plurality of exposed contacts that are formed from a common substrate material. The die attach pad, however, is thinned relative to at least a portion of the contacts. A die is mounted on the thinned die attach pad and wire bonded to the contacts. Since the die attach pad is lower than the contact surface being wire bonded to, the length of the bonding wires can be relatively reduced, thereby reducing inductance of the device. A plastic cap is molded over the die and the contacts thereby encapsulating the bonding wires while leaving the bottom surface of the contacts exposed. In some embodiments, the die is arranged to overhangs beyond the die attach pad towards the contacts.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: September 17, 2002
    Assignee: National Semiconductor, Corp.
    Inventors: Jaime Bayan, Peter Howard Spalding, Harry Cheng Hong Kam, Ah Lek Hu, Sharon Mei Wan Ko, Santhiran Nadarajah, Aik Seng Kang, Yin Yen Bong