Abstract: A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed.

Abstract: A truly complementary bipolar transistor structure and a combined bipolar and CMOS transistor structure are disclosed, each including a silicide layer formed upon a substrate that acts as an extrinsic base and gate. Optionally, a layer of polysilicon can be formed between the silicide layer and the substrate. An oxide layer (LTO) is formed or deposited over the silicide layer by chemical vapor deposition (CVD). Selected regions are defined and etched using a photoresist layer. Subsequent steps of implanting, etching and metalization are performed to produce transistors with reduced gate and extrinsic base resistances. Polysilicon may be used, instead of metal, as a contact in one embodiment of the invention.

Abstract: A bias control circuit and an associated method in an audio output amplifier provide slow turn-on or turn-off operation of a bias voltage generation circuit, using an external bypass capacitor. A slow rate in the turn-on and turn-off operations in such a bias voltage generation circuit prevents click or pop noises. In one embodiment, two bipolar transistors each responsive to the voltage on an external capacitor are provided to gradually increase the voltage of an output node, which can be used to drive the gate terminal of an MOS transistor in the bias voltage generation circuit. Alternatively, in another embodiment, an MOS inverter, which receives as input the voltage on bypass capacitor, is provided to divert current from a conventional bias circuit. The rate at which the MOS inverter diverts current from the conventional bias circuit controls the slew rate in the turn-off operation of the bias current.

Abstract: A jitter extraction circuit, which includes a cyclic phase differentiator, a control loop, and a jitter integrator, measures the jitter of a recovered clock signal formed from an incoming data bit stream. The phase differentiator differentiates a phase data word, which includes both a jitter component and a delta frequency component, to produce a differentiated phase data word. The control loop estimates and removes the delta frequency component to produce a filtered data word which primarily represents the jitter component. The jitter integrator recovers the original jitter component by integrating the filtered data word to produce a jitter data word. The jitter of the recovered clock signal is determined by the statistics of the jitter data words.

Abstract: A novel row decoder/driver circuit in which switched bias voltages are applied to the bulk regions in order to minimize the maximum voltage differential appearing across transistor devices. This allows the decoder/driver circuit to be conveniently fabricated and designed to allow normal transistors rather than more complex and expensive high voltage transistors, to form the row decoder/driver. The bulk regions containing the pull-up and pull-down transistors are biased by voltages which are switched during erasure depending on whether the row line is selected or deselected in order to assure that excessive voltages do not appear across based upon the voltage levels applied to the transistors.

Abstract: A PLL frequency synthesizer utilizes circuitry for altering pump current magnitude based upon division factors in the PLL. In one embodiment, pump current magnitude is responsive to the feedback division factor path, providing a constant gain over a wide frequency range, thereby providing a constant natural frequency and damping. In another embodiment, pump current magnitude is controlled as a function of both feedback and feedforward division factors, thereby maintaining a constant natural frequency with respect to the output frequency. In another embodiment, the output frequency is proportional to the VCO control signal raised to a power, with charge pump current controlled as a function of the feedforward division factor thus providing a natural frequency and damping factor which is constant with respect to output frequency. In another embodiment, gain control is provided as a function of at least one division factor in a PLL loop which does not utilize a charge pump.

Abstract: The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical columns of logic cells. The array further includes at least one horizontally aligned express bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned express bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array further includes at least one generally diagonally aligned local and/or express bus running between adjacent diagonally aligned logic cells, the adjacent diagonally aligned logic cells being connectable thereto.

Abstract: An input stage suitable for use with any desired supply voltage VCC, including supply voltages less than 5 volts, and which is capable of withstanding an overvoltage input signal greater than VCC applied to its input pad. A pass transistor is used between the input pad and the input buffer in order to limit the voltage supplied to the input buffer, thereby allowing voltages in excess of VCC to serve as a legitimate logical one input signal to the input buffer. Overvoltage protection is used to limit the voltage on the input pad to a voltage in excess of the greater-than-VCC legitimate input voltage. An output stage is suitable for use with a wide variety of supply voltages, including supply voltages less than 5 volts, while allowing proper operation in the event that a legitimate overvoltage is applied to its output pad. ESD protection is provided in order to limit the voltage on the output pad to a voltage greater than the maximum legitimate overvoltage.

Abstract: An electrically programmable nonvolatile semiconductor memory which includes an array of programmable transistor cells, such as EPROM cells, which avoids the use of field oxide islands to provide electrical isolation. The cells are arranged in X number of rows and Y number of columns with the cells in at least two of the rows being designated as select cells and the remaining cells being designated as memory cells. Control circuitry is provided for causing the select cells to supplying programming voltages to selected ones of the memory cells. Alternate ones of the select cells are initially programmed to a high threshold (inactive) state so as to provide electrical isolation for adjacent select cells which remain in the low threshold (active) state.

Abstract: An improved current source having high output impedance, low saturation voltage, and less sensitivity to process parameters is achieved by having enhancement P-channel transistor devices used as current mirror, while depletion P-channel transistor devices are provided as the cascode devices. A "diode connected" depletion device may be inserted between the enhancement gate and the drain of the current reference transistor to reduce saturation voltage. The "diode connected" depletion device keeps the drains of the enhancement devices at a similar voltage even when the enhancement and depletion device threshold, i.e. V.sub.T, do not track over temperature or process. Thus, the current mirror circuit provides not only higher output impedance, lower saturation voltage, but is also less sensitive to process variation.

Abstract: A gas distribution head for plasma deposition and etch systems includes an electrically conductive casing surrounding a plenum chamber. The casing includes a gas inlet and a gas outlet in the form of apertures through the casing. An electrically conductive electrode is positioned within the casing with respect to the interior surfaces of the casing such that a plasma forms between the electrode and the casing upon application of an electrical potential between them. A reactive gas is injected between the two electrodes which is struck to form a plasma for cleaning the inner surfaces of the plasma chamber of undesirable particulates and residues.

Abstract: In a method of bonding a pad on a semiconductor chip to a corresponding pad on a carrier, a wire ball is attached to the pad on the chip by bonding one end of a low melting temperature aluminum alloy bond wire to the chip pad. The wire is then broken off at the bond. A bead is formed on the chip pad by heating the ball to a temperature slightly above the melting point of the bond wire material for a predetermined period of time. The melted bead is then placed into contact with a corresponding pad on the carrier.

Abstract: A fuel composition sensor provides to a voltage divider comprising sensor and reference capacitors a voltage which oscillates between two voltages at a comparatively low frequency, such as 6 KHz, for lower power dissipation, but which switches fast to produce periodic fast voltage changes across the voltage divider to produce voltage spikes at the junction of the capacitors indicative of the capacitance ratio and thus of fuel composition.

Abstract: The present invention provides real time feedback interconnect system which allows real-time detection and control of bond force exerted on the bond site. A force sensor is provided in the bond system, which detects the bond force exerted by the bond tool. The force sensor provides a force signal to a real-time feedback circuit. The feedback circuit transmits a force adjustment signal to a z-motion actuator to adjust the force applied to the bond site.

Abstract: An ECL OR gate circuit, or a logical equivalent AND gate circuit, is provided whereby the input signals are both referenced to the same bias reference signal such that the propagation delay between each input port to the output port of the gate is substantially equivalent. Also provided is an improved ECL flip flop circuit using the ECL OR (or AND) circuit taught in accordance with the teachings of this invention for a faster ECL flip flop. In accordance with the teachings of this invention, a flip flop clock input signal is referenced to the same bias reference signal as the flip flop data input signal such that the propagation delay between the clock input to the output stage is substantially the same as the data input to the output stage.

Abstract: A novel circuit is taught to provide a smooth current transfer function over a range of two input voltages, so that power can be supplied to an electronic circuit from more than a single power source. In one embodiment such power sources include a battery and an DC supply operated off the AC mains. Associated with each such supply is a current source designed to provide a reference current. This reference current is used to establish mirror currents from each of the power leads in order to provide the desired output current.

Abstract: In a sample and hold circuit comprising a plurality of serially connected comparators wherein each comparator has a feedback switch coupled between an input terminal and an output terminal of the comparator, and wherein data is held on high impedance capacitive nodes, when the series of feedback switches turn off, a capacitor is coupled across a current switching transistor which has a control terminal coupled for receiving a feedback switch control signal. When the feedback switch control signal undergoes a transition, the capacitor causes a voltage to ramp up or down. A current limiting transistor having a control terminal coupled for receiving a delay control signal is coupled in series with the current switching transistor for controlling the rate of current flow through the current switching transistor in accordance with the magnitude of the delay control signal.

Abstract: An embedded modem that does not require a dedicated controller and operates with existing computer to interpret new and redefined communications interrupt requests. In response to an interrupt request, the control of the processor is transferred from the communications software to a driver program stored in the main memory for the processor. Under the operation of the driver program, the processor interprets control characters and causes the appropriate commands to be carried out in the modem. Once these commands have been processed, the control of the processor reverts back to the communications program. The processor thereby functions as a virtual controller that is interpreted to be an external controller by the communications program.

Abstract: An integrated circuit electronic grid device includes first and second metal layers wherein a layer of a dielectric medium is disposed between the metal layers. A third metal layer is disposed above the second metal layer and insulated from the second metal layer by another layer of a dielectric medium. The first and second metal layers are biased with respect to each other to cause a flow electrons from the first metal layer toward the second metal layer. The second metal layer is provided with a large plurality of holes adapted for permitting the flow of electrons to substantially pass therethrough and to travel toward the third metal layer. A fourth metal layer is disposed above the third metal layer to collect the electrons wherein the third metal layer is also provided with a large plurality of holes to permit the electrons to flow therethrough and continue toward the fourth metal layer.

Abstract: A thermally enhanced leadframe having heat conductive paths which thermally couple a die attach pad to thermal connection points spread out as far as possible from each other on the perimeter of the package. The area of the heat conductive path is maximized to occupy substantially all area in the package not occupied by the electrically conductive paths between the wire bond locations and the external connection points such as pins. This configuration maximizes the area of the printed circuit board which is heated thereby increasing thermal cooling efficiency. Further, the leadframe configuration maximizes the area of contact between the integrated circuit package and the heat conductive path thereby increasing the thermal conductivity between the device junctions on the integrated circuit die and the ambient through the material of the package itself.