Abstract: A repeater interface controller (“RIC”) integrated circuit with integrated filters and buffer drivers is provided for use in a repeater. In one embodiment, the RIC uses two filters to filter link pulse signals and data signals for a plurality of ports. Thus, the RIC is able to concurrently provide filtered link pulses to some ports and filtered data signals to other ports. Further, because only two filters are used, the area required to implement the plurality of ports is reduced relative to conventional repeaters that use a filter for each port. In another embodiment of the present invention, a RIC includes a logic circuit and a plurality of analog multiplexers and twisted pair buffer drivers. The analog multiplexers receive signals on their input lines and select which of these signals are passed to the buffer drivers to be outputted.

Abstract: A descriptor controlled transmit and receive scatter/gather Direct Memory Access Controller efficiently moves data frames comprised of scattered blocks of data from within memory to a destination interface via a multibyte-wide buffer. The transfer of frames into a transmit buffer and out of a receive buffer is optimized regardless of the total length of the component data blocks and regardless of whether the data blocks include an odd or even number of bytes, whether the data blocks begin at an odd or even address, or whether the data blocks are misaligned with regard to memory width boundaries. A DMAC in accordance with an embodiment of the present invention stores information provided by a descriptor before frame processing takes place. This information in conjunction with steering logic and accumulator registers is used to control the steering and storing of the frame data as it passes through the DMAC to the transmit buffer or from the receive buffer.

Abstract: Multiplication circuitry performs a multiply operation to multiply a multiplicand operand and a multiplier operand to form a total product of the multiplication operation, where the multiplier operand includes a plurality of multiplier operand portions. The multiplication circuitry includes multiplier circuitry configured to multiply each of the multiplier operand portions and the multiplicand operand, in a sequence, to form a sequence of partial products corresponding to the sequence of multiplier operand portions. The multiplier circuitry further includes combining circuitry configured, for each multiplier operand portion, to combine the partial product corresponding to that multiplier operand portion with a previous partial result, to generate a new partial result corresponding to that multiplier operand portion.

Abstract: A device in a phase-locked loop circuit that dynamically matches the currents in a charge pump to reduce the spurious tones during each charge pump event when the phase-locked loop is in lock. A regulator circuit is coupled to a first current source in a charge pump and is responsive to inverted up and down signals from a phase detector or to the currents of a charge pump. The integrator may adjust the first current to equal the second current when inverted up and down signals do not arrive at the regulator at the same time or when the loop filter voltage does not match the charge pump output voltage with both current sources of the charge pump are turned on but disconnected from the loop filter.

Abstract: A high-gain, high-bandwidth, low-noise differential common-emitter-common-base cascode preamplifier for use in the read circuitry of an MR head system includes a by-pass circuitry. Currents generated in load devices connected to the preamplifier are added to currents generated in the by-pass circuitry to provide the currents that flow through the common-emitter transistors of the preamplifier.

Abstract: Current-level monitoring circuitry incorporating a full-time coarse monitor and a part-time fine monitor and capable of generating control signals when the current-level being monitored reaches certain predetermined thresholds. In its preferred embodiment the invention is incorporated into battery-protection circuitry, guarding against both excess charging currents and excess discharging currents. A key concept of the invention is a hierarchical monitoring system incorporating a full-time coarse monitor that activates the fine monitor only when the battery current level enters a certain range and then deactivates it once the level falls out of that range again. Should the current level continue to rise up to the threshold of unsafe battery current, the fine monitor will disconnect the battery. In the preferred embodiment of the invention, the fine monitor operates by comparing, with a predetermined reference voltage, the voltage drop across a fine sensing resistor through which battery current is directed.

Abstract: A power management system pad clock and self-test circuit includes a clock processing circuit having a input configured to receive an oscillator clock signal having a first frequency. The clock processing circuit is configured to generate a first pad clock signal having a frequency approximately equal to one-half the first frequency and a second pad clock signal having a frequency that is equal to a programmable fraction of the first frequency. The circuit also includes a main pad clock output node. Multiplexer circuitry is coupled to the clock processing circuitry and the main pad clock output node and configured to receive a plurality of peripheral signals. The multiplexer circuitry is configured to operate in a standard mode of operation wherein one of the first pad clock signal and the second pad clock signal is routed to the main pad clock output node and a first test mode of operation wherein one of the plurality of peripheral signals is selectably routed to the main pad clock output node.

Abstract: A controller handles host commands from a host processor and also interfaces the host processor to a serial device. Storage circuitry (e.g., a shift register) of the controller holds a predetermined plurality of data bits. State machine circuitry controls the storage circuitry for serial bit-level communication (e.g., using a PS/2 protocol) between the storage circuitry and the serial device. A processor executes code from a program memory. In particular, the program code causes the processor to detect that a host command has been received by the controller from the host processor and causes an action corresponding to the host command received. Because the processor is not involved with the serial bit-level communication between the storage circuitry and the serial device, the processor executing the software can handle host commands without affecting the serial bit-level communication.

Abstract: A communication signal receiver performs a timing adjustment function of sampling with a circuit that also reduces the amount of electromagnetic interference (EMI) emitted from the receiver. The receiver includes an analog front end circuit that samples an input modulated carrier waveform responsive to a sampling clock signal to generate a digitized replica. The timing of the sampling is responsive to a timing signal. The digitized replica is analyzed to determine an appropriate adjustment to the sampling and, thus, to the timing signal. The frequency of the sampling is changed in accordance with the timing signal as adjusted, without adjusting the phase of the sampling. In particular, the frequency of the sampling is changed by removing transitions from an input clock signal to generate the sampling clock signal.

Abstract: A semiconductor device, polysilicon-contacted trench isolation- structure that provides improved electrical isolation stability, a method of operating a polysilicon-contacted trench isolated semiconductor device, and a process for manufacturing a polysilicon-contacted trench isolation structure. The trench isolation structure includes an isolation trench formed in a semiconductor substrate. The isolation trench has a layer of trench lining oxide, a layer of trench lining silicon nitride and a trench fill polysilicon (poly 1) layer. Exposed lateral surfaces of the poly 1, which extend above the trench lining silicon nitride, are contacted to another layer of polysilicon (poly 2). The method of operation includes applying a bias voltage to the trench fill poly 1 layer via poly 2. The process for manufacture includes etching an isolation trench that extends through a layer of field oxide and into a semiconductor substrate.

Abstract: A circuit that determines the remainder of a modulo 2 polynomial division in just one clock cycle. Specifically, each term of the remainder is determined in parallel with each other term of the remainder. The circuit includes a network of XOR devices to determine H(X)=P(X) mod G(X), where P(X) is a first binary polynomial, of a form: a.sub.m X.sup.m +a.sub.m-1 X.sup.m-1 30 . . . +a.sub.0, where a={0,1} and X={0,1}; G(X) is a second binary polynomial, of a form: a.sub.n X.sup.n +a.sub.n-1 X.sup.n-1 +. . . +a.sub.0, where a={0,1} and X={0,1}, and m>n; and H(X) is a third binary polynomial, of a form: b.sub.p X.sup.p +b.sub.p-1 X.sup.p-1 + . . . +.sub.0. The configuration of the network of XOR devices is determined by reducing terms of the first binary polynomial to have only terms having less than the degree of the second binary polynomial. Then, for each term of the third binary polynomial (i.e., the remainder), it is determined which reduced terms of the first binary polynomial affect it.

Abstract: A Universal Serial Bus hub circuit includes an upstream port and a plurality of downstream ports. The hub circuit further includes input circuitry via which data received on one of the downstream ports is to be repeated to the upstream port. Asynchronous event detection circuitry is to detect an asynchronous event in the received data for the one downstream port. Port selection circuitry to select the one downstream port. Timer circuitry is to measure a time period from a time that the asynchronous event detection circuitry detects an asynchronous event. Synchronous event detection circuitry is to detect a synchronous event in the received data for the one port. End-of-event generation circuitry generates a simulated end-of-event signal if the detected synchronous event is not before the end of the measured time period, and provides the simulated end-of-event signal to the upstream port.

Abstract: The accumulation of a small positive charge on the source of a MOS switch which occurs after the switch has been turned off due to the parasitic capacitance that exists between the gate and the source of the transistor, known as clock feedthrough, is reduced by utilizing a split-gate MOS transistor, and by continuously biasing one of the gates of the split-gate transistor.

Abstract: A method of fabricating an EEPROM cell structure in a semiconductor substrate includes forming a layer of silicon oxide having a first thickness on the silicon substrate. N-type dopant is then introduced into the semiconductor substrate to define a buried region beneath the silicon oxide layer. Next, a tunnel window opening is formed in the silicon oxide layer to expose a surface area of the buried region. A layer of tunnel oxide is then grown in the tunnel window opening on the exposed surface of the buried region, such that the tunnel oxide has a thickness that is less than the thickness of the silicon oxide. A first layer of polysilicon is then formed on the structure resulting from the foregoing steps, followed by an overlaying layer of oxide.backslash.nitride.backslash.oxide (ONO) and an overlying layer of second polysilicon. The poly-2, ONO.backslash.

Abstract: An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions.

Abstract: Embodiments according to the present invention provide tamper resistant structures which make it more difficult to reverse engineer integrated circuits. In one embodiment, a tamper resistant structure on a passivation layer leaves portions of the passivation layer exposed. Mechanical or chemical removal of the tamper resistant structure damages exposed portions of the passivation layer and makes reverse engineering difficult. Other embodiments of the tamper resistant structure include patterned and unpatterned structures containing hard materials, chemically resistant materials, amalgams, fibrous materials, and/or meshes attached to a passivation layer. Tamper resistant structures can also be provided between layers of the active circuitry.

Abstract: Digital circuits determine multiplicative inverses using look-up tables which, in response to an address signal, provide a signal indicating a multiplicative inverse. The look-up tables store values indicating inverses for numbers between 1 and 2. The circuit factors a value to be inverted as product a power of two and a factor between 1 and 2. An address signal indicating the factor is applied to the look-up table, and the look-up table provides a signal which indicates the inverse of the factor. The signal provided by the look-up table is then converted to the proper scale for the exponent N. Factoring and conversion may be accomplished with logical shifts so that no multiplier is required. The look-up table may be compressed by not storing bits of inverses, which are constant or only change once within the range of the look-up table and by only storing look-up values for every other number within the range of the look-up table.

Abstract: A multi-chip module interconnection substrate includes at least two layers of conductive traces separated by an intervening layer of insulating material. The conductive traces include straight segments and diagonal segments. A plurality of conductive vias, each including conductive via wing extensions, allow one to make electrical connections between the various conductive trace layers. The conductive vias are formed such that a narrow, non-conductive, gap exists between the via wing extensions and the conductive traces. The multi-chip module interconnection substrate is then programmed, e.g. in the field, by making electrical connections between the via wing extensions and the conductive traces using e.g. wire bonds or ball bonds formed by conventional wire bonding equipment.

Abstract: Two dimensional data structures are represented by quadtree codes with embedded Walsh transform coefficients. The quadtree code permits both variable block size inherent in quadtrees, and the calculational simplicity of Walsh transform descriptions of nearly uniform blocks of data. Construction of the quadtree is calculationally simple for implementation in a digital system which does a bottom-up determination of the quadtree because Walsh transform coefficients and a measure of the distortion can be recursively calculated using only Walsh transform coefficients from the previous level in the quadtree. Uniform step size quantization, which is optimal for variable length coding and generalized gaussian distributions, permits fast encoding and decoding of quadtree code.

Abstract: Input/output and local area network functions are combined into a single integrated circuit on a single semiconductor (e.g., a single piece of silicon). Preferred system embodiments on a single integrated circuit are typically placed inside a host system (e.g., a personal computer based on Intel.RTM.'s 286, 386, 486, and Pentium microprocessors) and interrelate with standard operating systems (e.g., Microsoft.RTM.'s DOS, IBM.RTM.'s OS/2) on traditional, commonly used bus architectures (e.g., Industry Standard Architecture and Enhanced Industry Standard). Local area network circuitry and input and output circuitry are both coupled to at least one host system (and indirectly to potentially any number of host systems tied together via the local area network system) via a common data bus. The input and output circuitry couples the host system to at least one input/output channels.