Abstract: The present invention provides a vertical punch-through cell comprising a silicon substrate, an epitaxial silicon layer overlying the substrate, an N+ buried column line formed at the interface between the substrate and the epitaxial layer, an N+ diffusion region formed above and spaced apart from the buried column line at the surface of the epitaxial layer, a field oxide layer formed over the epitaxial layer and having an contact opening formed therein over the N+ diffusion region, a polysilicon layer formed on the surface of the field oxide layer to extend through the contact opening to make contact with the N diffusion region, a layer of dielectric material formed over the polysilicon layer, and a layer of conductive material formed over the dielectric material.

Abstract: The present invention provides a single-poly electrically erasable programmable read only memory device which is formed in a semiconductor substrate of a first conductivity type. The memory device includes a pass cell comprising first and second regions of a second conductivity type, opposite to that of the first conductivity type, formed in the substrate. The first and second regions are separated by a first channel region formed by the substrate. A first conductive portion is formed over the first channel region and is separated from the first channel region by a dielectric material. A control cell comprising third and forth regions of the second conductivity type is also formed in the substrate. The third and forth regions are separated by a second channel region formed by the substrate. The first conductive portion extends over the second channel region and is separated from the second channel region by the dielectric material.

Abstract: Switched body circuitry is provided to prevent a system I/O from being effected by the loss of power supply or ground to an MOS integrated circuit within the system. A semiconductor substrate of a first conductivity type has formed therein a well region of a second conductivity type opposite to that of the first conductivity type. First, second, third and fourth spaced-apart shallow diffusion regions of the first conductivity type are formed at the surface of the well region. A first gate electrode and the second and third diffusion regions combine to form an MOS transistor which is either an input pull up or pull down device or an output pull up or pull down driver of the MOS circuit. A second gate electrode and the third and fourth diffusion regions combine to define a first MOS switched body transistor. A third gate electrode and the first and second diffusion regions combine to define a second MOS switched body transistor.

Abstract: A synchronizer circuit for recovering a clock signal from synchronizing strobes derived from a modulated dibit phase shift keying (PSK) input signal. A phase detector samples the output of a number controlled oscillator at synchronizing strobe intervals corresponding to zero crossings of the PSK input signal. The phase detector generates binary weighted outputs which are measured of the phase error between the number controlled oscillator and the synchronizing strobes.

Abstract: In a processor system with a virtual memory organization and a cache memory table storing the physical addresses corresponding to the most-recenty used virtual addresses, access to the cache table is enhanced by associating upper and lower MSB portions of a virtual address with corresponding upper and lower portions of an associated cache address. The separate cache address portions are placed in separate cache address storage devices. Each cache address storage device is addressed by respective virtual address MSB portions. A physical address storage device stores physical addresses translated from virtual addresses in storage locations addressed by cache addresses associated with the respective virtual addresses from which the physical addresses were translated.

Abstract: A circuit for producing a programmable phase shift of clock pulses in response to the data on a group of control lines. The circuit includes a ramp generator stage coupled to drive a comparator stage which has a reference potential input determined by the control line data. The phase shift can be employed to produce a series of subnanosecond delay increments on the clock pulses and is useful in the fine adjustment of a digital phase lock loop.

Abstract: Circuitry is provided for effectively cancelling the offset voltage of a differential reset stabilized latch. The circuitry preadjusts the voltage on the latch's amplifier dual input nodes prior to application of the signal voltage to the latch input such that the positive amplifier input voltage is substantially equal to the positive output voltage and the negative amplifier input voltage is substantially equal to the negative output voltage.

Abstract: A self-timed transition detector is provided that responds to a change in the logic level of a signal by generating a change-indicator flag. The change-indicator flag is held active until an event initiated by the change-indicator flag has been completed. Completion of the event cancels the change-indicator flag, thereby verifying the completion of the event.

Abstract: To cut a strip of metal into exact lengths, rollers are brought into contact with the strip and turned by an accurate motor until a pin can be mechanically inserted into a hole in the strip to effect final alignment. If the pin does not successfully enter the hole, a detector halts the system.

Abstract: This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity.

Abstract: This disclosure describes a recorder/playback system which utilizes a silicon chip having bipolar transistors. One feature is an integral electronic switching arrangement which permits silent and smooth change from the record to the playback mode and vice versa by operation of an external single pole switch. Other features include a circuit for driving a recording level meter, an automatic audio level control circuit (ALC) and integral voltage and current regulators.