Abstract: A voltage is provided by a master circuit and received by a plurality of slave circuits over a bus. The master circuit includes a V.sub.bb reference circuit, a temperature compensation and V.sub.cse reference circuit, and a voltage step-up and buffering circuit coupled to the bus. Each of the slave circuits has a pair of transistors coupled to the bus in an emitter-follower configuration to step down the voltage from the master circuit and to provide a voltage reference. The voltage provided to the bus varies as it propagates through the bus. Accordingly, a plurality of unconnected resistors are formed in the portions of the silicon substrate which contain the master and/or slave circuits. When formed in the master circuit, the resistors are located in the V.sub.bb reference circuit. When formed in the slave circuit, the resistors are located in close proximity to the output transistors.

Abstract: A differential phase shift keying (DPSK) modulator utilizes time-domain filtering techniques. The DPSK modulator includes a data scrambler which receives a serial digital data input signal and generates an output signal representing the dibit value of the serial input sequence. The dibit signal is differentially encoded and then provided to a history generator which produces phase modulating vectors utilizing pulse density modulation (PDM). The carrier waveform is then modulated utilizing the modulating vectors to generate a DPSK output signal.

Abstract: A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process includes the fabrication of buried layers 18 doped with both phosphorus and arsenic to permit a shorter diffusion time while simultaneously providing buried layers having low resistance and high diffusivity. The process enables fabrication of BiCMOS structures using only six masks prior to the contact mask.

Abstract: An adaptive gate charge circuit for switching a power FET on in response to a control signal. The adaptive gate charge circuit includes driving circuitry that responds to assertion of a control signal by providing a charging current from a charge pump reservoir capacitor to the gate of the power FET for an initial time period sufficient to switch the power FET on. After the initial time period, holding circuitry provides holding current from the charge pump to the power FET gate to compensate for charge leakage. Current limiting circuitry connected to the holding circuitry limits current drain from the charge pump after the initial time period to the holding current required to compensate for charge leakage plus a minimum additional current.

Abstract: A PLA is formed using configurable logic elements. A plurality of pages are used to store information defining logic configuration patterns required to perform desired logical functions. The configurable logic elements are configured by downloading information from a desired one or more of said pages. If desired, page control is achieved in response to input signals to the configurable logic array.

Abstract: An adaptive gate discharge circuit for discharging the gate of a power FET transistor. The adaptive gate discharge circuit includes discharge driver circuitry which responds to the control signal by discharging the power FET gate from the initial "on" potential of the power FET to below a selected potential at which the power FET is turned off. During gate discharge, but prior to the potential of the power FET gate dropping below the selected potential, adaptive bias circuitry continues to operate to provide biasing current both to the discharge driver circuitry as well as to any other circuitry it may be biasing. However, when the potential of the power FET gate drops below the selected potential, low current biasing circuitry reduces the operating voltage of the adaptive biasing circuitry thereby turning off the adaptive biasing circuitry and any other circuitry it may be biasing.

Abstract: A current limiting circuit (200, 300, 400) for instantaneously limiting the peak current of a fast high side power switch (212) or power FET has a reference switch (213) or FET, a first comparator (218), a current source I.sub.CL, control circuitry (209), and a clamping circuit (238). The reference FET (213) is smaller than the power FET (212). The first comparator compares the voltage drop across the power FET (212) and compares it with the voltage drop across the reference FET (213) and produces a signal COMPOUT which initiates the turn-off of the power FET (212) if the voltage drop across the power FET (212), caused by a load current flowing through it, is greater than or equal to the reference FET voltage drop induced by I.sub.CL. The clamp circuit (238), having diodes (D.sub.1, D.sub.2) and a tracking current source I'.sub.CL, disconnects the FETS (212, 213) from the comparator (218) when they are OFF.

Abstract: Preamble smoothing for information character transmissions in a data transmission network is accomplished as follows. First, the smoothing filter identifies the start of a new preamble. If the start of a new preamble is identified and a previously received preamble has been extended, then the preamble is contacted by deleting an IDLE byte or, if the frame received prior to the initial IDLE byte was a frame fragment, then the information character preceding the initial IDLE byte is deleted. Following the contraction of the preamble, a determination is made as to whether next received byte is an IDLE byte. If it is not, then the preamble is extended by inserting an IDLE byte and the smoothing filter begins searching for the start of a new preamble. If it is, then a counter is incremented. If the counter has not yet reached its preset threshold, then the next byte is checked to determine whether it is an IDLE byte. If it is, then the counter is again incremented.

Abstract: A multi-port, BI-CMOS memory cell is disclosed having a CMOS flip-flop, one or more write ports gated by n-channel FETs, and one or more ECL read ports. Bipolar transistors in the read port are resistively interconnected to equalize emitter voltages during write and standby operations and to resistively isolate the emitters during a read operation.

Abstract: A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution.

Abstract: An EEPROM device provides increased speed and less susceptibility to soft writes during reading and programming operations. A unique circuit design and operating method obviates the need for applying a high programming or erase voltage in the path between the memory array and sense amplifier. Such high programming and erase voltages are applied, as needed, directly to the memory array, thereby allowing all transistors which carry signals from the memory array to the sense amplifier to be fabricated as low voltage devices, thereby increasing their speed of operation and thus the speed of operation of the memory device as a whole. By applying the relatively high programming and erase voltages to the source of the memory transistors, and reading from the drain of the memory transistors, the source and drain as well as associated circuitry are fabricated to optimize their intended functions.

Abstract: An electrostatic discharge protection circuit without the use of a series resistor is described. MOSFET transistors with a turn-on voltage above the postive supply voltage but below the breakdown voltage are used. In one embodiment, parasitic bipolar transistors formed in conjunction with the MOSFETs are employed for further protection.

Abstract: Clock select circuitry is provided which allows CPU operation at the crystal frequency or one-half the crystal frequency. Frequency selection is accomplished under CPU control and circuitry is added to insure that the a glitch free clock change can be performed on the fly. The glitch free clock select insures that no half T state is less than what a full speed half T state would be. By gating the appropriate phases of the half speed clock and the full speed clock to control the clocking of a flip flop, the point at which the clock selection multiplexer is switched can be controlled. In speeding up the clock, the speed change occurs on the falling edge of the full speed clock provided that the half speed clock is low. When slowing down the clock, the speed change occurs on the rising edge of the half speed clock.

Abstract: A PLA is organized into a plurality of pages of programmable logic arrays, including means for selecting an appropriate set of one or more of the plurality of pages of programmable logic arrays, including means for selecting an appropriate set of one or more of the plurality of pages for operation at any given time. Means are provided for switching pages when necessary in response to input signals including, if desired, signals fed back from the output leads of the PLA, or internal leads within the PLA. By having only a selected one or more of the pages of the PLA operable at any given time, the number of product and sum terms functioning at any given time is significantly less than the total number of product and sum terms available in the device, thereby minimizing power consumption. Furthermore, by utilizing a paged architecture, speed is increased and power consumption reduced since the number of leads connected to, and thus the capacitance of, the product and/or sum term lines is reduced.

Abstract: An architecture and device for testing mixed analog and digital VLSI circuits, wherein the digital circuit portions of the chip are grouped into a digital block, and the analog circuit protions of the chip are= grouped into an analog block. Analog signals are provided to the digital block through an A/D transducer, and digital signals are provided to the analog block through a D/A transducer. The analog and digital blocks may be isolated from each other by a digital input multiplexer disposed between the A/D transducer and the digital block, and by an analog input multiplexer disposed between the D/A transducer and the analog block. To minimize the number of pins required to implement the architecture, multiplexers are connected to accessed circuit nodes in the analog block and the digital block for selectively communicating signals from the accessed nodes to external output pins.

Abstract: A 16-bit adder architecture configured uniquely as two 8-bit adders. The first 8-bit adder uses a static technique to perform addition of the least significant bits and a dynamic technique to perform addition on the remaining bits. The second 8-bit adder uses a static technique to perform addition of the most significant bits and a dynamic technique to perform addition on the remaining bits. The two 8-bit adders are combined at the most significant bit of the first adder and the least significant bit of the second adder using the carry out of the first adder and the carry in of the second adder. A static logic gate is used to logically combine and correctly time the combination of the two 8-bit adders into a single, high-speed 16-bit adder.

Abstract: The present invention provides a timing recovery technique for baseband-coded data sequences which applies to line codes with inband timing information embedded in periodic signal transitions, such as zero-crossings. The technique utilizes a selection of data patterns, like mark-to-mark, which have zero-crossings at the "center" of a transition from a positive to negative mark. These so-called "bipolar patterns" consist of two polar-signals of opposite polarity sharing neighborly baud intervals. Because the random nature of a data sequence gives timing information a statistical behavior, a timing recovery system recovers a timing average, the efficiency of the system being given in terms of the timing variance. According to the present invention, a low variance estimate for the bipolar-pattern-center timing signal is obtained by proper filtering.

Abstract: According to the teachings of this invention, a novel sense amplifier is provided which includes a current steering transistor having its emitter connected to the collector of a current mirror transistor, its collector connected to the base of an output transistor, and its base driven by the input signal. With a low input signal, the emitter of the current steering transistor is pulled low, thereby pulling the base of the output transistor low. Conversely, when the input signal is high, and the current steering transistor ceases to operate in the active saturation mode and begins to operate in the inverse active saturation mode, thereby providing current from its base to its collector in order to turn on the output transistor.

Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead.The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communications station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.

Abstract: A programmable sense amplifier in accordance with the present invention includes an input multiplexer which receives a plurality of data input signals from the column lines of a ROM and provides a selected one of a data input signals as a data output signal based on control signals proviced to the input multiplexer. The voltage level of the data output signal corresponds to the number of 1's contained in the selected column line. A sensing stage receives the data output signal and amplifies it. The amplified signal is then provided to an XOR gate which either does or does not invert the amplified signal, based upon the state of the select node to which one of the XOR gate inputs is connected. The state of the select node is determined by a programmable internal multiplexer. The internal multiplexer comprises a number of FET switching transistors corresponding to the number of data input signals. Each of the switching transistors has one of its electrode areas commonly-connected to the select node.