Abstract: A suitable inert thermal gas such as argon is introduced onto the backside of wafers being processed in a CVD reactor during the deposition of tungsten or other metals and silicides, to avoid deposition of material on the backside of the wafers being processed. Each process station includes a gas dispersion head disposed over a platen. The platen has a circular depresssion for receiving a wafer, and an annular groove provided in the floor of the depression, near the wall thereof. Heated and pressurized backside gas is introduced into the groove so that the wafer is maintained in a position above the floor of the depression but still within it. In this manner, backside gas vents from beneath the edge of the wafer on the platen and prevents the process gases from contacting the wafer in a transfer region above the platen, so that the wafer can be transported to or from the platen with a suitable wafer transfer mechanism.

Abstract: An optical interconnect structure, formed on a substrate, optically interconnects optoelectronic transmitting and receiving devices. The optical interconnect structure includes optical interconnects each of which includes a core member constructed of a material having a first predetermined index of refraction. The ends of the core members are chemically bonded either to an optoelectronic device or a core member of another optical interconnect. A cladding layer surrounds each core member. Each end of a cladding layer proximate to an optoelectronic device is chemically bonded to that device. The cladding layer is formed of a material having a second predetermined index of refraction, the magnitude of which is less than the magnitude of the first predetermined index of refraction.

Abstract: A logic level control circuit prevents impact ionization in a CMOS integrated circuit. The substrate bias voltage of the CMOS integrated circuit is detected by the control circuit and a control signal is provided in response to the detected bias voltage. The bias voltage can be zero volts or negative five volts. If the bias voltage is zero volts, the control signal is a logic level one. If the bias voltage is negative five volts, the control signal is a logic level zero. The control signal is applied to the gate of at least one other controlled device on the integrated circuit for turning the controlled device on and off. The controlled device coupled to a further CMOS device and turning the controlled device on and off prevents impact ionization by allowing the controlled device to alternately divide a voltage level with the further CMOS device or be effectively removed from the circuit.

Abstract: There is disclosed a structure for self aligned and non-self aligned power and ground buses and interconnects for integrated circuits which are thicker than normal conductors. This enables them to withstand higher current densities without adverse electromigration effects. There is also disclosed a method for making such structures.

Abstract: A thin film capacitor for use in an integrated circuit includes a lower plate disposed on the silicon substrate of the integrated circuit. The lower plate comprises a barrier layer of conductive material which prevents transport of silicon from the silicon substrate into a layer of dielectric material which is disposed between the lower plate and an upper plate. A portion of the barrier layer can be consumed and transferred into dielectric material by, for example, high temperature oxidation which generates a symmetric series capacitor with the dielectric layer. A layer comprising an oxide of the barrier layer material is formed between the barrier layer and the dielectric layer by consuming an upper portion of the barrier layer.

Abstract: A method and structure for forming in an EEPROM memory transistor a tunnel dielectric region having an extremely small surface area. A floating gate region is formed in the conventional manner above a gate dielectric layer. The drain region is exposed utilizing photolithographic techniques and the gate dielectric removed therefrom. A thin layer of tunnel dielectric is then formed on the exposed drain region. A thin layer of polycrystalline silicon is then formed and etched in order to create very narrow floating gate extensions of polycrystalline silicon along the edge of the previously formed floating gate. The floating gate extension formed in this manner which overlies the drain region is separated from the drain region by thin tunnel dielectric. A dielectric is then formed on the device in order to provide a dielectric over the drain region which has a greater thickness than the tunnel dielectric underlying the floating gate extension.

Abstract: A technique for operating a common emitter circuit from a plurality of supply voltages. In one embodiment, a current mirror includes a plurality of diode-connected transistors each connected between a source of current and associated supply voltages. Corresponding current mirrors are each connected between an output terminal associated supply voltage leads, thereby providing an output current mirrored from the soure of current, regardless of which of the supply voltages are activated, and regardless of their particular levels. In another embodiment, a regulator includes an output transistor having a plurality of current handling terminals, each connected to an associated supply voltage, and a second current handling terminal coupled to an output terminal.

Abstract: An integrated circuit device is fabricated upon a semiconductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.

Abstract: The surface of a semiconductor wafer is planarized by disposing the wafer in a wafer plane and rotating the wafer within the wafer plane wherein the rotation is around an axis perpendicular to the plane. A stream of particles is transported to the surface of the wafer while the wafer is rotating wherein the angle between the stream of particles and the wafer plane is small. The stream of particles mills the surface of the wafer thereby planarizing the surface of the wafer. The angle between the stream of particles and the wafer plane is preferably less than thirty degrees. The particles may be argon ions and may be chemically active particles or physical particles.

Abstract: A bilayer mask is utilized for etching a primary layer, which may be either an aluminum metallization layer or a dielectric layer. The bilayer mask includes both a thin resist layer and a metal imaging layer. The thin resist layer provides for high resolution patterning of the metal imaging layer. The metal imaging layer, in turn, provides for durability to withstand subsequent plasma etching of the underlying primary layer.

Abstract: An output buffer circuit advantageously uses a simple integrated circuit package including two separate ground leads for connection to an externally supplied ground voltage. The relatively large pull down current which passes through the pull down transistor of one or more output buffers are fed through a first ground lead of the lead frame to the external ground and the remaining circuitry is connected to the external ground through the second ground lead of the lead frame. The transients in the pull down current will cause ground bounce which affects the pull down transistor only, and not the remaining components of the output buffer. In this manner, base drive to the output pull down transistor is not decreased due to ground bounce, and the high to low transition of the output voltage is not degraded by the presence of ground bounce. In an alternative embodiment, the amount of ground bounce is controlled to provide a desired characteristic of the output transition.

Abstract: A PLA is formed using configurable logic elements. A plurality of pages are used to store information defining logic configuration patterns required to perform desired logical functions. The configurable logic elements are configured by downloading information from a desired one or more of said pages. If desired, page control is achieved in response to input signals to the configurable logic array.

Abstract: An integrated circuit package includes a plurality of TAB assemblies, each including a portion for inner lead bonding an integrated circuit. A portion of the tape is formed to allow the tape to be outer lead bonded to the substrate so that the integrated circuit is mounted at any desired non zero angle with respect to a horizontal substrate. A plurality of formed tape units are outer lead bonded to a horizontal substrate. In one embodiment, the die is inner lead bonded to the tape in an area which is not devoid of tape, allowing electrical traces on the tape which are routed above and not in contact with the surface of the die, thereby providing excellent routing density. The dielectric tape may include a single electrical interconnect layer, or a plurality of electrical interconnect layers which may themselves be electrically interconnected via suitable vias formed within the tape structure.

Abstract: An encryption method is taught which chooses certain bytes of data, stored in a particular on-chip memory, as encryption keys. These chosen bytes are used to encrypt themselves, and all of the remaining data in the above mentioned particular memory. The chosen bytes do not have values specifically assigned for encryption, they are merely chosen, according to a rule, from the body of data to be encrypted. When this technique is implemented, each byte of data, stored in the mentioned memory, is combined (for example using an exclusive NOR gate) with one of the designated encryption key bytes prior to disclosure. The user is not required to provide, program, or safeguard a set of key bytes separately. Additionally, no silicon area is wasted in storing such bytes. An intruder would need certain pieces of the original data in order to decipher the results of this encryption technique. Additionally, this technique degrades gracefully.

Abstract: The present invention provides for a sense amplifier having a pair of input nodes connected through isolating PMOS transistors to the differential input terminals of the amplifier. Each of the input nodes is also connected to the gates of a pair of carefully matched NMOS transistors and to the drain of the other of the matched pair. In addition, each of the input nodes is connected to the gate of one of two drive NMOS transistors. The drains of the drive NMOS transistors are each connected to the gates of two output PMOS transistors, the drains of which form the output terminals of the sense amplifier. The sources of the matched NMOS transistor pair are coupled to ground by a NMOS transistor and the sources of the drive NMOS transistors are coupled to ground by another NMOS transistor. When the differential signals at the input terminals are to be sensed and latched, the sources of matched transistor pair and the sources of the drive transistors are sequentially connected to ground.

Abstract: A programmable logic device is constructed having a novel architecture. A plurality of control input signals are applied to a programmable mapping array in order to generate control functions for data path gating, latching, or modification. The programmable control functions provide flexibility to the designer, while the fixed data path logic is independent of the programmable array. The logic array and data path logic are fabricated on the same integrated circuit, therefore obviating the need for input/output buffers which would be necessary if the device were constructed utilizing discrete components. This enhances the performances of the device. Since the data path does not travel through the array, its performance is not affected by the programmability. If desired, the programmable array can be formed of mask programmable devices, fused programmable devices, or register based circuitry, for example, using RAM cells.

Abstract: A novel voltage selection circuit in which only one of a plurality of voltage levels is selected for application to an output node at any given time. Switching transistors are connected between the output node and associated reference voltages. Switching transistors are controlled by a set of voltage selection signals, each having logical zero and logical one states which are of sufficient magnitude to cause said switching transistors to turn on or turn off, and which are insured to be nonoverlapping. Two of the voltages are ground and VCC, which are switched by associated transistors using voltage selection signals having standard levels, such as ground and VCC. Another voltage VPPP is greater than VCC, and is switched by a switching transistor utilizing a voltage selection signal greater than VCC, preferably equal to VPPP. The wells of the second and third switching transistors are connected in common to VPPP to prevent junction breakdown when VPPP is selected.

Abstract: A bilayer mask is utilized for etching a primary layer, which may be either an aluminum metallization layer or a dielectric layer. The bilayer mask includes both a thin resist layer and a metal imaging layer. The thin resist layer provides for high resolution patterning of the metal imaging layer. The metal imaging layer, in turn, provides for durability to withstand subsequent plasma etching of the underlying primary layer.

Abstract: An integrated circuit package includes a plurality of TAB assemblies, each including a portion for inner lead bonding an integrated circuit. A portion of the tape is formed to allow the tape to be outer lead bonded to the substrate so that the integrated circuit is mounted at any desired non zero angle with respect to a horizontal substrate. A plurality of formed tape units are outer lead bonded to a horizontal substrate. In one embodiment, the die is inner lead bonded to the tape in an area which is not devoid of tape, allowing electrical traces on the tape which are routed above and not in contact with the surface of the die, thereby providing excellent routing density. The dielectric tape may include a single electrical interconnect layer, or a plurality of electrical interconnect layers which may themselves be electrically interconnected via suitable vias formed within the tape structure.

Abstract: An adaptive equalizer for compensating input signal frequency and phase distortion introduced in the input signal transmission media is provided. The adaptive equalizer includes frequency selection means for generating an output signal of a selected frequency in response to the input signal and a feedback signal. A comparator slices the equalizer output at predetermined levels. A controller receives the comparator output and provides a controller output representative of the voltage level of the comparator output. A digital filter receives the controller output and generates a corresponding binary signal as the feedback signal to the frequency selection means.