Patents Assigned to NEC Electronics Corporation
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Publication number: 20100224874Abstract: A TCP-type semiconductor device has: a base film; a semiconductor chip mounted on the base film; and a plurality of leads formed on the base film and electrically connected to the semiconductor chip. Each of the plurality of leads has a test pad section at a position other than both ends of the each lead.Type: ApplicationFiled: March 2, 2010Publication date: September 9, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Suguru Sasaki
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Publication number: 20100224914Abstract: Provided is a semiconductor device including: a first n-channel fin-type field effect transistor formed on a first crystal plane; and a second n-channel fin-type field effect transistor formed on the first crystal plane and having a gate length longer than that of the first n-channel fin-type field effect transistor. A side surface of a fin of the first n-channel fin-type field effect transistor and a side surface of a fin of the second n-channel fin-type field effect transistor are both formed on a second crystal plane having a carrier mobility lower than that of the first crystal plane. The width of the fin of the second n-channel fin-type field effect transistor is greater than the width of the fin of the first n-channel fin-type field effect transistor.Type: ApplicationFiled: March 2, 2010Publication date: September 9, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: Toshiyuki IWAMOTO, Gen TSUTSUI, Kiyotaka IMAI
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Publication number: 20100224995Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.Type: ApplicationFiled: May 4, 2010Publication date: September 9, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
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Probe card, semiconductor testing device including the same, and fuse checking method for probe card
Publication number: 20100225343Abstract: A probe card according to an exemplary aspect of the present invention includes: a force terminal supplied with a first power supply voltage; a probe needle that supplies a voltage corresponding to the first power supply voltage to a semiconductor integrated circuit to be tested; a fuse connected in series on a first signal line which connects the force terminal and the probe needle; and a fuse check circuit that supplies a voltage different from the first power supply voltage supplied from the force terminal, to a first node located on a signal line between the probe needle and one end of the fuse. The circuit configuration enables checking of a connection state of a fuse prior to product inspection. This makes it possible to perform semiconductor testing with high reliability.Type: ApplicationFiled: February 16, 2010Publication date: September 9, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Takayuki Kouno -
Publication number: 20100229057Abstract: The test circuit can apply a stress to each node of each object combinational circuit in the semiconductor device and suppress the semiconductor circuit overhead when in burn-in or leak test operations for the semiconductor device while it has been impossible to apply such a stress to any of such nodes only with use of an F/F circuit in any conventional environments. The test circuit is disposed in the semiconductor and combined with first and second combinational circuits therein. In the semiconductor device, a transfer gate switch is connected between first and second nodes and a first transistor is connected between the second node and a power supply. The second transistor is connected between the second node and a ground. Each of the transfer gate switch and the first and second transistors operates according to at least one of the control signals supplied from outside the semiconductor device.Type: ApplicationFiled: February 22, 2010Publication date: September 9, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Satoshi Ishizuka
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Publication number: 20100225330Abstract: An object of the present invention is to provide a method of testing an electric fuse which enables to reduce a time for testing. The method of testing an electric fuse according to the present invention comprises: selecting a plurality of disconnection-targeted fuses among a plurality of electric fuses; disconnecting a plurality of disconnection-targeted fuse blocks in tern, each of which includes at least one disconnection-targeted fuse; electrically connecting one terminal of each of the plurality of disconnection-targeted fuses to a first node and connecting another terminal of the each disconnection-targeted fuse to a second node, after disconnecting; and judging whether or not all of said plurality of disconnection-targeted fuses are disconnected after electrically connecting, by applying a voltage to the first node to judge whether or not a current flows between the first node and the second node.Type: ApplicationFiled: March 2, 2010Publication date: September 9, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Naotake Watanabe
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Publication number: 20100225331Abstract: A continuity testing apparatus includes open/short detection circuits provided for to-be-tested terminals, respectively and configured to determine the presence or absence of at least any one of an open-circuit failure and a short-circuit failure in to-be-tested terminals. Then, the continuity testing apparatus generates detected results of the open/short detection circuits based on the condition of continuity of the to-be-tested terminals having connections to the open/short detection circuits and the detected results from the open/short detection circuits in the preceding stages, and outputs the generated detected results to the open/short detection circuits in the succeeding stages. Further, the continuity testing apparatus determines the condition of continuity based on the output from the open/short detection circuit in the last stage.Type: ApplicationFiled: March 4, 2010Publication date: September 9, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: Hiroyuki Fuchigami, Shouichirou Satou
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Publication number: 20100225377Abstract: A switch circuit includes an input section; an output section; a first series section having an output and comprising at least a first 4-terminal FET connected between the input section and the output section through the output of the first series section; a first shunt section comprising at least a second 4-terminal FET connected between an output of the first series section and a ground; a first control terminal section connected with a gate of the first 4-terminal FET; a second control terminal section connected with a gate of the second 4-terminal FET; and a back gate control terminal section connected with a back gate of each of the first and second 4-terminal FETs. A bias power supply section is configured to apply a reverse bias voltage between the back gate control terminal section and the ground.Type: ApplicationFiled: March 5, 2010Publication date: September 9, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Tomonori OKASHITA
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Publication number: 20100224941Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel suicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.Type: ApplicationFiled: June 5, 2007Publication date: September 9, 2010Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Kazuya Uejima, Hidetatsu Nakamura, Akihito Sakakidani, Eiichirou Watanabe
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Publication number: 20100229144Abstract: An operation synthesis system includes an operation synthesizing section configured to perform operation synthesis of an operation description to generate a data path graph corresponding to the operation description, wherein the data path graph contains an input terminal configured to input an input data and an operating unit configured to perform an operation on the input data; and a gating circuit inserting section configured to insert a gating circuit between the input terminal and the operating unit. The gating circuit blocks off transmission of the input data from the input terminal to the operating unit when the operating unit does not need the input data, and transmits the input data from the input terminal to the operating unit only when the operating unit needs the input data.Type: ApplicationFiled: March 4, 2010Publication date: September 9, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Takahide EZAKI
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Publication number: 20100225516Abstract: A semiconductor device includes: input terminals identified by channel numbers and configured to receive analog signals; analog input pads identified by pad numbers and connected with whole or part of the input terminals; a data holding section configured to hold a data of the input terminals; a channel designating section configured to generate a channel designation signal to designate one of the channel numbers; and a channel translating section configured to translate the channel number indicated by the channel designation signal into a specific one of the pad numbers based on the held data. An A/D converting section is configured to convert the analog signal inputted from the analog input pad corresponding to the specific pad number into a digital signal.Type: ApplicationFiled: March 1, 2010Publication date: September 9, 2010Applicant: NEC Electronics CorporationInventor: Souichirou Ishibuchi
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Publication number: 20100226190Abstract: An SRAM includes a memory cell; and a control circuit configured to change a signal level of a signal which is used in an ordinary mode for access to the memory cell in a test mode to apply a disturbance to the memory cell. The control circuit can change the signal level to set a level of the disturbance optionally.Type: ApplicationFiled: February 3, 2010Publication date: September 9, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Hiroyuki KOBATAKE
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Publication number: 20100228993Abstract: A USB interface apparatus is provided in electronic equipment on a USB packet transmission side, and includes a conversion unit for converting CRC object data which is data contained in a field subjected to CRC calculation in a USB packet, based on a predetermined rule corresponding to reverse conversion of conversion to be performed on the CRC object data by destination electronic equipment; a CRC calculation unit for calculating a CRC of CRC object data obtained before conversion by the conversion unit; and a packet generation unit for generating a USB packet containing data converted by the conversion unit and the CRC calculated by the CRC calculation unit.Type: ApplicationFiled: March 1, 2010Publication date: September 9, 2010Applicant: NEC Electronics CorporationInventor: Takayuki Suzuki
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Patent number: 7791186Abstract: A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.Type: GrantFiled: October 4, 2006Date of Patent: September 7, 2010Assignees: NEC Corporation, NEC Electronics CorporationInventors: Katsumi Kikuchi, Shintaro Yamamichi, Yoichiro Kurita, Koji Soejima
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Semiconductor device including a coupling region which includes layers of aluminum and copper alloys
Patent number: 7791198Abstract: An improved reliability in a region of a junction between a bonding wire and an electrode pad at higher temperature is achieved. A semiconductor device 100 includes a semiconductor chip 102, AlCu pads 107, which are provided in the semiconductor chip 102 and which contain Al as a major constituent and additionally contain copper (Cu), and CuP wires 111, which function as coupling members for connecting inner leads 117 provided outside of the semiconductor chip 102 with the semiconductor chip 102, and primarily contain Cu. The AlCu pads 107 and the CuP wires 111 are encapsulated with an encapsulating resin 115 that contains substantially no halogen.Type: GrantFiled: February 4, 2008Date of Patent: September 7, 2010Assignee: NEC Electronics CorporationInventors: Takekazu Tanaka, Kouhei Takahashi, Seiji Okabe -
Patent number: 7791040Abstract: Aimed at providing an ion implantation apparatus elongated in period over which failure of a target work, due to deposition and release of ion species typically to and from the inner surface of a through-hole shaping a beam shape of ion beam, may be avoidable, reduced in frequency of exchange of an aperture component, and consequently improved in productivity, an aperture component shaping a beam shape has a taper opposed to the ion beam, in at least a part of inner surface of at least the through-hole, and has a thick thermal-sprayed film formed so as to cover the inner surface and therearound of the through-hole.Type: GrantFiled: July 23, 2008Date of Patent: September 7, 2010Assignee: NEC Electronics CorporationInventors: Minoru Ikeda, Toshio Iida
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Patent number: 7791371Abstract: A level shift circuit includes a drive transistor, a first PMOS transistor, and first and second clamp transistors of PMOS type. The drive transistor, which drives the gate of the high-side NMOS transistor in a power semiconductor device, has a source-drain path coupled between a boot potential generated by a bootstrap circuit provided in the semiconductor device and a source potential of the high-side NMOS transistor. The first PMOS transistor has a source coupled to the boot potential, and a drain coupled to the gate of the drive transistor. The first clamp transistor has a gate coupled to the source potential of the high-side NMOS transistor, and a source coupled to the drain of the first PMOS transistor. The second clamp transistor has a gate coupled to the source potential of the high-side NMOS transistor, and a source coupled to the gate of the first PMOS transistor.Type: GrantFiled: June 5, 2009Date of Patent: September 7, 2010Assignee: NEC Electronics CorporationInventor: Koichi Nakazono
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Patent number: 7793174Abstract: A SiP includes a logic chip and a memory chip. The memory chip includes a memory circuit to be tested, and the logic chip includes an internal logic circuit and a test processor electrically connected therewith. The test processor is connected with an access terminal of the memory circuit and supplies a test signal input from an external terminal to the access terminal to thereby test the memory circuit. The test processor includes a high-speed test control circuit to adjust signal delay and supplies a test signal from the external terminal to the access terminal through the high-speed test control circuit when performing high-speed test at an actual operation speed.Type: GrantFiled: March 16, 2007Date of Patent: September 7, 2010Assignee: NEC Electronics CorporationInventors: Takashi Hattori, Yumiko Hashidume, Tatsuhiro Nishino, Kouji Ikeda
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Patent number: 7790579Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.Type: GrantFiled: April 6, 2006Date of Patent: September 7, 2010Assignee: NEC Electronics CorporationInventors: Kohji Kanamori, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
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Patent number: 7793092Abstract: Configuration codes for implementing a plurality of circuits having different attributes are generated and stored in a memory for each task executed in a reconfigurable device. When the reconfigurable device is operated, an appropriate circuit to be executed by the reconfigurable device is selected in accordance with an operation state of the system from among a plurality of circuits having different attributes, and the configuration code for implementing the selected circuit is loaded from the memory into the reconfigurable device.Type: GrantFiled: December 27, 2006Date of Patent: September 7, 2010Assignees: NEC Corporation, NEC Electronics CorporationInventors: Takao Toi, Tooru Awashima, Hirokazu Kami, Takeshi Inuo, Nobuki Kajihara, Taro Fujii, Kenichiro Anjo, Koichiro Furuta, Masato Motomura
