Abstract: The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holes 103 extending through the silicon substrate 101 is provided. An insulating film 105 is buried within the through hole 103. A plurality of columnar through plugs 107 are provided in the insulating film 105.

Abstract: A method for forming a plurality of gate patterns in parallel with each other on a photoresist layer within a circuit block includes forming extension gate patterns on both ends of the gate patterns and on both ends of a dummy gate pattern of the circuit block to reach an edge of the circuit block, and performing a first photolithography process upon the photoresist layer by using a phase shift photomask having first and second openings whose difference in phase is ?, the first and second openings alternating between the gate patterns including the extension gate patterns to form phase edges therein.

Abstract: Provided is an integrated circuit including: multiple memory cells; a redundant memory having a function of repairing a defective cell included in the multiple memory cells by placing a corresponding fuse among multiple fuses into a first state; a fuse data conversion circuit that generates first information of a first defective cell based on position information of the fuse placed into the first state corresponding to the first defective cell having been repaired; a repair data generation circuit that generates, upon detection of a second defective cell as a result of a test for the multiple memory cells, repair information for repairing the second defective cell according to the first information and second information of the second defective cell; and a fuse state change circuit that places a predetermined fuse among the multiple fuses into the first state according to the repair information generated by the repair data generation circuit.

Abstract: An image processing method prepares image data having luminance information (Y) and chrominance information (UN) including first chrominance information (U) being information of a color difference between a blue component and luminance and second chrominance information (V) being information of a color difference between a red component and the luminance. The method then outputs the luminance information and the chrominance information in the image data forming a first frame as data forming the first frame, and further outputs the luminance information in the image data forming a second frame subsequent to the first frame and the chrominance information in the image data forming the first frame as data forming the second frame.

Abstract: A page table management circuit includes a memory control circuit including a memory unit that stores information used to convert a virtual address into a physical address with respect to each entry and designating the entry according to an input address value, and an address conversion circuit converting an input address value such that a total number of the entries to be designated by the memory control circuit is reduced and outputting the converted address value to the memory control circuit.

Abstract: In order to suppress variation of a resist pattern size caused by a temperature unevenness at a prebaking process, applying a resist of a positive type or a negative type on a base substrate, prebaking, exposing, post-exposure baking, and forming the resist to be a predetermined shape by developing the resist are carried out. The prebaking is carried out at a temperature equal to or more than a detachment starting temperature of a protective group of a base resin included in the resist in a case where the resist is the positive type. In a case where the resist is the negative type, the prebaking is carried out at a temperature equal to or more than a cross-linking starting temperature of a cross-linker in a base resin included in the resist.

Abstract: A first mobile terminal forming a mobile communication system connects to a base station by using a first wireless communication method (for example, GSM method). Further, a second mobile terminal acquires unique information of the base station (for example, cell information) from the first mobile terminal by communication with the first mobile terminal by using a second wireless communication method (for example, wireless LAN method), and searches a transmission frequency of the base station included in the unique information.

Abstract: A current control circuit in accordance an exemplary aspect of the present invention includes a first transistor that controls a current flowing to a load, a first resistor through which a current flows according to a current flowing through the first transistor, a control signal generation circuit that generates a control signal used to control the first transistor based on a comparison voltage and a predetermined reference voltage, the comparison voltage being determined based on a resistance value of the first resistor and a current flowing through the first resistor, and a reference voltage generation circuit that generates the reference voltage, the reference voltage generation circuit including a constant current source and a second resistor connected in series with the constant current source.

Abstract: A method of manufacturing a semiconductor device, includes 5 steps. The first step is a step of forming a floating gate on a first surface region of a semiconductor substrate through a gate insulating film. The second step is a step of forming a tunnel insulating film so as to cover a second surface region adjacent to the first surface region and an end portion of the floating gate. The third step is a step of forming an oxide film so as to cover the tunnel insulating film and be thicker at a portion above the second surface region than at a portion above the floating gate. The fourth step is a step of etching back the oxide film and a surface of the tunnel insulating film on the floating gate. The fifth step is a step of forming a control gate on the tunnel insulating film on the second surface region.

Abstract: An amplifying device comprises a first amplifying unit (91-97) capable of changing its gain in a stepwise manner, a second amplifying unit 99 cascade-connected to the first amplifying unit (91-97), the second amplifying unit being capable of changing its gain in a stepwise manner, and a gain controller 100 controls the gain setting of the first amplifying 91-97 unit and the second amplifying unit 99. The first amplifying unit has a gain variable range necessary to amplifying the input signal to the prescribed desired level. The second amplifying unit has a gain variable range narrower than that of the first amplifying unit. When the gain controller changes the gain setting, the gain controller uses the second amplifying unit preferentially over the first amplifying unit.

Abstract: A method of manufacturing a nonvolatile semiconductor memory includes: forming an insulator structure on a semiconductor substrate in a first region; forming a first gate insulating film on the semiconductor substrate outside the first region; blanket depositing a first gate material film and etching-back the first gate material film to form a first gate electrode on the first gate insulating film lateral to the insulator structure; removing the insulator structure; blanket forming a second gate insulating film; blanket depositing a second gate material film and etching-back the second gate material film to form a second gate electrode on the second gate insulating film in the first region; and silicidation of upper surfaces of the first and second gate electrodes. Any one of the first and second gate insulating films is a charge trapping film.

Abstract: A semiconductor device includes a field-effect transistor on a substrate. The field-effect transistor includes a gate insulating film and a gate electrode. The gate electrode has a laminated structure including a first electrode layer made of a first metal, a second electrode layer made of a second metal, and a third electrode layer made of a silicon layer. The second metal is a material having a workfunction for alleviating band discontinuity between the first electrode layer and the third electrode layer, with respect to a majority carrier of the silicon layer.

Abstract: The semiconductor device of the present invention includes a first interconnection, a via-plug that is connected to the first interconnection, and a second interconnection that is formed as a single unit with the via-plug. The cross-sectional shape of the via-plug is such that the plug sidewall angle, which indicates the angle of the via-plug sidewall with respect to the surface of the first interconnection, is a positive angle; and moreover, at least two points exist between the base and the top of the via-plug on at least one sidewall of the two sidewalls of the cross-sectional shape of the via-plug at which the plug sidewall angle attains a maximum value. Since shapes that would give rise to the occurrence of concentrations of stress are not formed in the via-plug sidewalls, metal is more effectively embedded in the via-hole, and the incidence of voids is prevented.

Abstract: A semiconductor integrated circuit device includes a first field-effect transistor and a second field-effect transistor, each of the first field-effect transistor and the second field-effect transistor having a gate electrode formed as a ring shape, a drain diffusion layer formed inside the gate electrode and a source diffusion layer formed outside the gate electrode and a substrate potential diffusion layer or a well potential diffusion layer disposed to contact each of the source diffusion layers of the first and the second field-effect transistors of the same conductivity type, the substrate potential diffusion layer or the well potential diffusion layer being formed with a semiconductor of a different conductivity type from the source diffusion layer.

Abstract: In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.

Abstract: A solid-state imaging apparatus includes a pixel array comprising a plurality of light receiving elements disposed in a charge transfer direction, the plurality of light receiving elements converting a light signal into an electric signal, a first charge transfer unit and a second charge transfer unit arranged on each side of the pixel array and transferring a signal charge input from the pixel array in the charge transfer direction, a first floating diffusion region connected to the first charge transfer unit, a second floating diffusion region connected to the second charge transfer unit, a wiring layer connecting the first floating diffusion region with the second floating diffusion region, and an output circuit connected to the wiring layer and output a signal voltage in accordance with a potential of the first floating diffusion region and the second floating diffusion region.

Abstract: The solid-state imaging device includes a semiconductor substrate and a light receiving portion. On the back surface of the semiconductor substrate a contact surface is provided. The solid-state imaging device photoelectrically converts, in the semiconductor substrate, light transmitted through the object to be imaged in contact with the contact surface, and receives the electric charge generated by the photoelectric conversion with the light receiving portion, to thereby acquire the image of the object to be imaged. The contact surface is a rough surface.

Abstract: A clock distribution circuit, which is provided in IC that has a first sequential circuit receiving first clock through a first branch node on a first clock network, a second sequential circuit receiving second clock through a second branch node on a second clock network, and a data transfer path between the first and second sequential circuits, includes: a first PLL receiving a first feedback clock that is the first clock branched at the first branch node and outputting the first clock to the first clock network based on the first feedback clock; and a second PLL receiving a second feedback clock that is the second clock branched at the second branch node and outputting the second clock to the second clock network based on the second feedback clock. A branch node is provided at least one of between the first PLL and the first branch node and between the second PLL and the second branch node.

Abstract: An OTP memory cell according to the present invention includes: a semiconductor substrate including a lower electrode forming region having a lower electrode formed therein, a diffusion layer forming region having a source and a drain formed therein, a first trench-type insulating region, and a second trench-type insulating region; an upper electrode being in contact with the first trench-type insulating region and formed on the lower electrode with the first insulating film interposed therebetween; and a gate electrode being in contact with the second trench-type insulating region and formed on a channel region with the second insulating film interposed therebetween, in which a shape of at least a part of an end of the lower electrode forming region in contact with the first insulating film is sharper than a shape of an end of the channel region in contact with the second insulating film.

Abstract: To provide a semiconductor device capable of securely executing a reading operation to improve a reliability of read data, an IC tag including the semiconductor device, and a control method for the IC tag. A semiconductor device according to an embodiment of the present invention includes: a power supply voltage generating circuit for generating a power supply voltage based on a received radio signal; a power supply voltage generating circuit for detecting the power supply voltage; a memory area for storing predetermined data; a reading/writing circuit using different operation voltages for reading data from the memory area and writing data to the memory area; and a control circuit for executing a data reading operation for the memory area based on a detected power supply voltage.