Abstract: A method of operating a liquid crystal display device includes: (A) time-divisionally driving pixels in a certain line of an LCD panel so that pixels adjacent in a horizontal direction are driven with data signals of opposite polarities. The (A) step includes: (A1) generating a first data signal of a first polarity on a first output terminal of a driver, and then driving a first pixel out of said pixels in the certain line through electrically connecting the first output terminal to the first pixel; and (A2) generating a second data signal of the first polarity on the first output terminal and then driving a second pixel out of said pixels in the certain line through electrically connecting the first output terminal to the second pixel, in succession to the drive of the first pixel.

Abstract: A semiconductor device according to an embodiment of the present invention includes an output stage circuit including a first conductive type first transistor and a second conductive type second transistor, the first conductive type first transistor being connected between a first power supply terminal and an output terminal, the second conductive type second transistor being connected between a second power supply terminal and the output terminal and having a leak current larger than that of the first transistor, and an input stage circuit outputting a logic value setting the first transistor to a non-conductive state and setting the second transistor to a conductive state in accordance with a logic circuit disable signal input when the output stage circuit is in a disable state.

Abstract: An optical module includes a receptacle for receiving an optical connector attached to a distal end of an optical fiber, and a lens body having a contact surface coming into contact with the distal end of the optical fiber when the receptacle receives the optical connector. The lens body has the contact surface and an opposing surface opposing the contact surface, and further has a columnar base held by the receptacle, a lens portion formed on the opposing surface integrally with the base, and a flat portion. The lens portion is surrounded by the flat portion and is off-centered with respect to the base.

Abstract: A structure analysis apparatus (1) for analyzing structure of a complex material layer containing a plurality of members (2a, 2b) for modeling layout data on a complex material layer, includes: an area setting portion (21) for setting an area to be modeled in the complex material layer; an area dividing portion (22) for dividing the area into a plurality of elements; an area computing portion (23) for calculating, based on an occupancy of each of the plurality of members (2a, 2b) in the area, the number of elements corresponding respectively to the plurality of members (2a, 2b); and an element placing portion (24) for generating a model of the complex material layer by placing the plurality of members (2a, 2b) respectively in the plurality of elements based on the number of the elements corresponding respectively to the plurality of members (2a, 2b).

Abstract: A data processing apparatus includes a non-volatile semiconductor memory configured to store a storage data and an additional data control circuit configured to generate an additional data and add the additional data to a main storage data, and the additional data is different between a first mode and a second mode. The additional data control circuit includes a first mode circuit configured to generate the additional data in the first mode; and a second mode circuit configured to generate the additional data in the second mode. The storage data contains a target data or an inversion data of the target data, as the main storage data and the additional data.

Abstract: Provided is a semiconductor integrated circuit capable of testing power control operation in the semiconductor integrated circuit including a power controllable region. Power control switches have switch series each constituted by a plurality of switch cells. A power controllable region includes output nodes in the switch series. The output nodes output power control signals that have passed through final stages of the respective switch series of the power control switches to the outside of the power controllable region. A chip on which the semiconductor integrated circuit is mounted has output terminals that output outputs of the output nodes to the outside of the chip. In the case of inserting a scan path test, observation flip-flops that load the outputs of the output nodes to data terminals, and load scan data to scan-in terminals are disposed in correspondence with the respective output nodes. Those observation flip-flops are connected to constitute a scan path chain.

Abstract: There are provided a signal detection process that derives coordinates in a device coordinate system in analysis data for abnormal signal data included in the analysis data of a semiconductor integrated circuit obtained from a semiconductor inspection apparatus; a coordinate conversion process that derives a correspondence between a coordinate in the device coordinate system and a coordinate in a design coordinate system in the design data of the semiconductor integrated circuit for a plurality of reference points in the semiconductor integrated circuit, and that derives a coordinate conversion formula between the device coordinate system and the design coordinate system; an error calculation process that derives a position error between a coordinate in the device coordinate system converted by the coordinate conversion formula and a coordinate in the design coordinate system; and a circuit extraction process that extracts a circuit related to the abnormal signal in the design data based on the coordinates of

Abstract: Provided is an intermediate potential generation circuit with a lower power supply potential. The intermediate potential generation circuit includes: a current mirror circuit including a first transistor and a second transistor each having a source input with a power supply potential; a current source circuit including a third transistor having a drain connected to a drain of the first transistor; a grounded source amplifier circuit including a fourth transistor having a gate input with the intermediate potential, and a drain connected to a drain of the second transistor; a parallel connection circuit including a fifth transistor connected in parallel with the first transistor, and a sixth transistor connected in parallel with the second transistor; and a source follower circuit including a seventh transistor and an eighth transistor having gates that are connected in common to each other, and connected with the drains of the second transistor and the sixth transistor.

Abstract: A semiconductor storage device includes a level shift unit that shifts level of potential of bit line pair BL, BLB when a sense amplifier starts to read potential of the bit lines. The level shift unit includes level shifting capacitors and a timing generator. Each of level shifting capacitors have one electrode connected to each bit line and form one pair by two level shifting capacitors for each bit line pair. The timing generator is connected to each of the other electrodes of the level shifting capacitors in common, and supplies a shift capacitor drive signal to a common node of the other electrodes, so as to change stored electricity amount of the level shifting capacitors at a predetermined timing.

Abstract: An improved SIV resistance and an improved EM resistance are achieved in the coupling structure containing copper films. A semiconductor device includes: a semiconductor substrate; a second insulating layer formed on or over the semiconductor substrate; a second barrier metal film, formed on the second insulating film, and being capable of preventing copper from diffusing into the second insulating film; and an electrically conducting film formed on the second barrier metal film so as to be in contact with the second barrier metal film, and containing copper and carbon, wherein a distribution of carbon concentration along a depositing direction in the second electrically conducting film includes a first peak and a second peak.

Abstract: Disclosed is a display controlling apparatus including latch circuits for holding color data of a current line and a previous line, a latch circuit for holding a polarity signal of the previous line, and a recovery control circuit. The recovery control circuit controls a recovery switch from color data of the previous and current lines, a polarity signal and a recovery clock. For both driving method employing frame-based common inverting and the driving method employing line-based common inverting, the display/controlling apparatus recovers electric charge efficiently to provide for low power dissipation.

Abstract: Method for manufacturing a semiconductor device including a semiconductor substrate, an element formed on the substrate, and an insulating film formed on the element, includes: (a) forming a first conductive layer (b) forming a first insulating film on the upper portion of the first conductive layer; (c) forming a second insulating film with a porous structure on the first insulating film; (d) forming a third insulating film different from the second insulating film on the second insulating film; (e) forming a via hole in the second and third insulating film by dry etching of the third insulating films; (f) removing a part of the first insulating film such that the surface of the first conductive layer is exposed at the bottom of the via hole and (g) forming a second conductive material film layer so as to fill the via hole.

Abstract: A simulation system includes an input acceptance unit that accepts a measured dimension of a transfer pattern; a calculation unit including a light intensity calculation unit that calculates a light intensity at each position, and a modified light intensity calculation unit that adds a modified value including the product of the light intensity and a tentative optical reaction coefficient to the light intensity, thereby giving a modified light intensity; and a decision unit that decides the threshold value and optical reaction coefficient by regression calculation such that a difference between the measured dimension and the calculated dimension becomes minimal under the modified light intensity, with a constant being the threshold value of the light intensity at a pair of edges defining the calculated dimension of the transfer pattern in the simulation.

Abstract: A liquid crystal display apparatus is composed of an LCD panel including data lines, and an LCD driver. The LCD driver includes: a positive drive circuit providing a positive data signal having positive polarity with respect to a ground level of the LCD driver for one of the data lines; and a negative drive circuit providing a negative data signal having negative polarity with respect to the ground level of the LCD driver for another one of the data lines.

Abstract: The present invention provides an interrupt generation circuit that can reduce the time between the moment a monitored object actually enters a desired state and the moment an interrupt is generated. An external event detection unit 101 detects the effective edge of an external event signal. A count period generation circuit 103 generates external event division signals which are counted by the main timer 104 and each of which has a period that is 1/N of the time interval between the effective edges of the immediately preceding external event signal. A compare register 105 stores a value corresponding to the time at which an interrupt is to be generated. When the count value of the main timer 104 becomes equal to or larger than the value stored in the compare register 105, the interrupt determination circuit 106 generated an interrupt.

Abstract: An integrated circuit including: a bus system including a bus master connected to a bus; and a memory controller connected to the bus system and controlling a connection between the bus master and a memory, in which the bus system includes a counter counting a waiting time from a time the bus master outputs a memory access request until a time a connection between the bus master and the memory controller is established, and the memory controller controls a memory access based on the waiting time counted by the counter.

Abstract: In a conventional solid state imaging device, there is a room for improvement in sensitivity. In order to solve the problem, a solid state imaging device includes a semiconductor substrate and a light receiving portion. The light receiving portion is provided adjacent to a surface layer on the surface (a first surface) side of the semiconductor substrate. The surface of the light receiving portion is silicided. The solid state imaging device is one in which light from an object to be imaged incident on the back side (a second surface) of the semiconductor substrate is photoelectric-converted inside the semiconductor substrate, the light receiving portion receives electric charge generated by the photoelectric conversion, and the above mentioned object to be imaged is imaged.

Abstract: There is provided a memory module that facilitates meeting the needs of high-speed performance and large capacity. It comprises first module substrates (101 through 108), each with multiple DRAM devices (11), and a second module substrate whereon the first modules (101 through 108) are mounted, signal line groups connected to the multiple first modules respectively are provided in parallel, and a controller LSI (50), connected to the multiple first modules respectively via the signal line groups provided in parallel, that converts the signal lines into fewer signal lines than the total number of the signal line groups and outputs the result is provided, and the second module substrate (20) is mounted on a motherboard (40).

Abstract: A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.

Abstract: A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with the reference voltage and output a boost operation control signal according to a comparison result, and a booster to generate the applied voltage in a pulse-like voltage waveform by starting or stopping boost operation based on the boost operation control signal. The applied voltage corresponding to the first voltage upon inversion of the boost operation control signal is varied within one pulse-like voltage waveform by varying one of the first voltage and the reference voltage.