Abstract: A semiconductor memory device includes a memory cell array, an ECC (error correction code) circuit and a decision circuit. The ECC circuit calculates an error correction code for write data to be written in the memory cell array. The decision circuit invalidates the ECC circuit when a data width of the write data is less than a predetermined data width.

Abstract: A data line driving circuit includes a first buffer circuit configured to drive a data line, and a second buffer circuit configured to drive a data line. N first data lines (n is a natural number larger than 1), and m second data lines (m is a natural number larger than 1) are alternately arranged in units of data lines as a group. The data line driving circuit further includes a first switch circuit configured to select one of the n first data lines in a first ON period and to connect the selected first data line with the first buffer circuit, and a second switch circuit configured to select one of the m second data lines adjacent to the selected first data line in a second ON period and to connect the selected second data line with the second buffer circuit.

Abstract: A lateral MOSFET according to the present invention has a trench gate structure having a cross sectional shape spreading toward an open end. The cross sectional shape is T-shape. The T-shaped cross section has a dimensional ratio of a width of a lower trench having a narrow width to a width of an upper trench having a wide width of 1:3, and a dimensional ratio of a depth of the lower trench to a depth of the upper trench of 1:1, the lower trench width having a same central axis as the upper trench width.

Abstract: The present invention includes a plurality of mounting portions on which a semiconductor element is mounted, a plurality of electrodes to which the semiconductor elements that are mounted on each of the mounting portions are electrically connected, a corner portion which connects the plurality of mounting portions and which has a hanging lead piece that supports the mounting portions and an electrode connection piece that connects the plurality of electrodes, and a half-blanking portion that has a concave portion formed in a thickness direction of the lead frame and a protrusion formed at a position corresponding to the concave portion, and which is covered with a sealing resin material that seals the semiconductor element. A stress-dispersing portion for dispersing stress that arises, when the half-blanking portion is formed, is provided in the corner portion.

Abstract: An evaluation pattern for evaluation of lateral hillock formation is provided with a lattice pattern; and an isolated metallization. The lattice pattern includes: a loop interconnection; and lattice interconnections laterally and vertically arranged to intersect with one another so that a region surrounded by the loop interconnection is divided into a plurality of sub-regions arranged in rows and columns. The width of the lattice interconnections is narrower than the width of the loop interconnection. The isolated metallization is provided in an outmost one of the sub-regions, the outmost one being surrounded by the loop interconnection and corresponding ones of the lattice interconnections.

Abstract: An operational amplifier includes a differential amplifier input stage that supplies an operating current to a differential pair, the differential amplifier input stage including a first transistor having a first polarity, a push-pull amplifier output stage that includes a second transistor having the first polarity, and a third transistor having a second polarity, the second transistor and the third transistor being connected in series, and a capacitive element that connects a gate of the first transistor and a gate of the second transistor.

Abstract: A power supply voltage detection circuit of the present invention includes a reference signal generation circuit that generates a reference signal according to a power supply voltage, a first transistor having a current flowing between a first terminal and a second terminal, where the current is controlled according to the reference signal, a voltage generation circuit that generates a control voltage according to a potential difference between the power supply voltage and the first terminal of the first transistor, and a second transistor that controls whether or not to output the power supply voltage according to the control voltage. Such circuit configuration enables to accurately detect a low voltage state of the power supply voltage.

Abstract: There is provided a semiconductor integrated circuit including a scan path circuit, which includes an encryption data storage unit that stores a secret key B created by encrypting a chip ID with use of a secret key A, and an encryption circuit that encrypts output data of the scan path circuit based on the secret key B and outputs the encrypted output data. This circuit configuration enables an increase in confidentiality in encryption of a scan test result.

Abstract: The extent of a bow of a semiconductor device is suppressed in a case where the fillet width of an underfill resin is asymmetrical. The center position 12 of a chip 1 is caused to deviate from the center position 13 of a wiring substrate 2 in a direction (the direction of the arrow B) reverse to the deviation direction (the direction of the arrow A) of the center position 11 of an underfill resin 4 from the center position 12 of the chip 1. The center position 14 of a resin for encapsulation 6 is caused to deviate from the center position 13 of the wiring substrate 2 in the same direction (the direction of the arrow A) as the deviation direction (the direction of the arrow A) of the center position 11 of the underfill resin 4 from the center position 12 of the chip 1.

Abstract: Second-conductivity-type high dose impurity layers are formed in a device forming region, and function as the source and drain; a second-conductivity-type low dose impurity layer is provided around each of the second-conductivity-type high dose impurity layers so as to expand each second-conductivity-type high dose impurity layer in the depth-wise direction and in the direction of channel length, at least a part of the second-conductivity-type low dose impurity layer is positioned below the gate electrode, and the gate insulting film; and the gate insulating film has, at a portion thereof positioned above the second-conductivity-type low dose impurity layer, a sloped portion which continuously increases in the thickness from the center towards a side face of the gate electrode, without causing an inflection point.

Abstract: A semiconductor storage device in accordance with an exemplary aspect of the present invention includes a plurality of memory cells arranged in a matrix pattern, a plurality of word lines each provided so as to correspond to each line of the memory cells, a plurality of bit lines each connected to respective one of the memory cells, and a row selection circuit that, in a read operation, drives the word line to a set potential at a drive speed slower than a discharge speed of the bit line exhibited when the word line is raised roughly vertically to VDD.

Abstract: In a semiconductor device, corner portions of a inner insulating film are chamfered, and hence a damage is less likely to reach the corner portion of the inner insulating film, though the corner portion of an outer insulating film is damaged. Therefore, a hermeticity of a semiconductor element can be effectively maintained, and the yield of semiconductor pellets can be improved. Moreover, since it is not necessary to chamfer the corner portion of the outer insulating film, the structure remains simple and the productivity can be improved.

Abstract: A buffer circuit outputs a low voltage and high voltages as opposed logic signals and a first high voltage and a second high voltage that is higher than the first high voltage as the high voltages.

Abstract: A disconnection detecting method includes charging a capacitor by connecting a node of the capacitor to a first power source line supplied with a first power source potential, connecting the node of the capacitor to an input terminal, after the node of the capacitor is disconnected from the first power source line, and converting a first value on the node to a first digital data. The method further includes discharging the capacitor by connecting the node of the capacitor to a first power source line supplied with a second power source potential, after the node is disconnected from the input terminal, connecting the node of the capacitor to the input terminal, after the node of the capacitor is disconnected from the second power source line, and converting a second value on the node to a second digital data.

Abstract: An object of the present invention is to provide a highly accurate delta sigma A/D converter. Disclosed is a delta sigma A/D converter including: a first integration circuit to generate a first signal on the basis of an input signal and a first feedback signal from an output side; a first signal conversion circuit to convert the first signal into a first converted signal; a loop delay compensation circuit to generate a compensation signal and then to output the compensation signal in response to a second feedback signal fed back from the output side at a timing earlier than that of the first feedback signal; an adder circuit to add the first converted signal and the compensation signal; and a comparator to generate a digital signal on the basis of an output signal from the adder circuit. The loop delay compensation circuit includes a compensation signal conversion circuit to generate the compensation signal.

Abstract: Provided are a semiconductor device capable of reducing a difference in wiring resistance between paths from a gate pad to a gate electrode and capable of applying a gate voltage to the gate electrode more uniformly, and a method of manufacturing the semiconductor device. The semiconductor device according to an exemplary aspect of the present invention includes a gate pad supplied with a gate voltage applied to a gate electrode of each MOSFET cell disposed in an active region, a gate connection line connected to the gate pad, and a plurality of gate lead-out lines connected in parallel between the gate electrode and the gate connection line. Each of the plurality of gate lead-out lines has a resistance value that becomes smaller by every one or plural gate lead-out lines as the gate lead-out lines are located farther away from the gate pad.

Abstract: To provide an LDPC decoder, to which SPA is applied, and a method wherein decoding characteristics are improved by reducing the ratio of a message from a check node within messages sent to the same check node. In a decoding device that decodes a received LDPC code by repeating the passing of messages between a plurality of check nodes and a plurality of bit nodes corresponding to a check matrix in each iteration, the order of message computation at a cluster in an iteration out of at least two iterations that have a before-and-after relationship in time and the order of message computation at a cluster in another iteration are varied.

Abstract: A semiconductor device contains an interposer having a square planar geometry, with length X for a first edge and length Y for a second edge orthogonal to the first edge, and a semiconductor chip and a dummy component disposed over the interposer, wherein the center of a first outer circumferential region, which surrounds the semiconductor chip over the interposer, and has length “a” for a third edge, and length “b” for a fourth edge, does not coincide with the center of the interposer, or equation X:Y=a:b is not satisfied, and the center of a second outer circumferential region, which surrounds the first outer circumferential region and the dummy components disposed over the interposer, and has length “x” for a fifth edge, and length “y” for a sixth edge, coincides with the center of the interposer, and equation X:Y=x:y is satisfied.

Abstract: A multi-source MOS transistor includes a sense MOS transistor and a load MOS transistor, and is connected to a load. A current detection portion has a negative input offset voltage characteristic, and detects a first sense current in a state where it is connected to the power supply and the sense MOS transistor and a second sense current in a state where it is connected to the sense MOS transistor and the load MOS transistor. A calculation control portion calculates a load current based on the first sense current and the second sense current such that the effect of the input offset voltage in the current detection portion is cancelled.

Abstract: An SC-type optical receptacle includes a first and a second holder each having a hollow chamber longitudinally penetrating therethrough, and a hollow cylindrical sleeve fitted in the chamber of the holders to thereby retain the frontal facets of a pair of ferrules so as to keep the frontal facets butted to each other. The wall thickness of the sleeve is constant over the entire length thereof, and is not less than 0.55 mm.