Abstract: A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test pattern set from the change input and the initialization scan chain test pattern.

Abstract: A method and system for use in wafer fabrication systems. The method and system identify relationships among constituent parts of a wafer fabrication system by generating a presentation of at least one relationship between an identified at least one integral part associated with the wafer fabrication system and at least one other integral part associated with the wafer fabrication system.

Abstract: A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing a burst transfer include determining the starting address of the vector data to be transferred, the ending address of the vector data to be transferred, and whether the ending address of the vector data to be transferred is within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined based on the number of data elements to be transferred, the stride of the vector data to be transferred, and the width of the vector data elements to be transferred. When the amount of data to be transferred is divisible by a factor of two, the multiplication of the stride and width of the data elements is carried out by shifting.

Abstract: A method and system for use in wafer fabrication systems. The method and system identify wafer fabrication system impacts resulting from specified actions by specifying at least one action related to at least one integral part associated with the wafer fabrication system, and generating a presentation of at least one impact upon at least one integral part associated with the wafer fabrication system arising from the at least one action related to the at least one integral part associated with the wafer fabrication system.

Abstract: Described is a data processing system including a processor, a plurality of caches, and main memory, the secondary caches being implemented as being non-inclusive, i.e., the lower order caches not storing a superset of the data stored in the next higher order cache. The non-inclusive cache structure provides increased flexibility in the storage of data. The operation of a write request operation when the target data line is not found in the primary cache. By using the dirty bit associated with each data line, the interaction between the processor and the primary cache can be reduced. By using the invalidity bit associated with each data line, the interaction between the processor and the primary cache can be reduced.

Abstract: A source magnet assembly for an ion source system of an ion implantation system. The source magnet assembly includes source magnetic poles that are operationally movable with respect to an arc chamber of the ion source system. In one example, the magnetic field produced by the source magnet is positionable in a two dimensional area. In another example, the magnetic field can be rotated. Some source magnet assemblies include plates that are slidable with respect to one another. The magnetic core is moved by moving the plates with respect to each other by a motorized force. With some assemblies, structures of the assembly are rotatable with respect to one another so that the core may be rotated around the arc chamber.

Abstract: The present invention provides a bus architecture for a data processing system that improves transfers of vector data using a vector transfer unit (VTU). An external bus is coupled between the vector transfer unit and the memory. The external bus includes a system command bus that is used to transmit a data transfer command. The command is based on a corresponding vector transfer instruction in the application program, such as load vector data or store vector data. The commands for transferring the data elements include a burst read command and a burst write command. A variable number of data elements may be transferred, according to the user's requirements. The system command bus is also capable of transmitting a packing ratio that indicates the number of data elements that fit in the width of the external bus. This allows the entire bandwidth of the external bus to be used during vector data transfers.

Abstract: An apparatus and method for simultaneously cycle-testing two wafer storage containers is provided. The two wafer containers are maintained in a counterbalance relationship to each other and cycled in a vertical up-and-down motion to simulate the forces of a selected overhead transport system.

Abstract: An apparatus and method for distributing dopant gas or vapor in an arc chamber of ion source used as part of an ion implanter. The apparatus includes a plenum, a sub-plenum, and a baffle to distribute the dopant gas or vapor through out the arc chamber. The method allows dopant gas and vapors to be distributed in such a way as to cause efficient reaction of dopant gas or vapor molecules with electrons created by a filament contained in the arc chamber. The reaction of dopant gas or vapor molecules with the electrons in turn produces positively charged ions by the ion implanter.

Abstract: A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector instructions are used for transferring the vector data between memory and registers used to perform calculations on the vector data. The transfers of portions of the vector data required in a calculation are scheduled so that calculations on a portion of the vector data are performed while a subsequent portion of the vector data is transferred. A vector buffer pool is partitioned into one or more vector buffers based on configuration information including the number of vectors buffers required by an application program and the size required for each vector buffer. The vector buffers are allocated for exclusive use by an application program that is executing in the data processor. Vector data transfer instructions are posted in a vector transfer instruction queue and are executed in the order they are posted to the instruction queue.

Abstract: The invention utilizes the linear complexity of orthogonal vectors to reduce the number of equations (or variables) to be solved. The present invention constructs a power model of a set of combinations of states without considering irrelevant combinations. The invention distinguishes between the switching direction on the input and the output pin. The invention considers state-dependency as a function of power consumed and depending on the paths through internal nodes. The model considers switching input pins that do not cause the output pin to switch to overcome inaccuracies caused by combining the power pin model with the state and arc power model with state. The model considers switching input pins that cause the output pin to switch. For cells in which the slewrate propagation effect from input to output is negligible, the invention uses a model of 2 power pins with state. The invention also determines the validity of this model.

Abstract: In one embodiment, a file of all the initial states (or their equivalents) and the nth surviving states associated with the initial states is stored along with the path metric. The initial states (or their equivalents) are an index to a previous file. A.new file or files are then generated. An appropriate criterion is utilized to select a final surviving state. The path can be traced back through a plurality of files and the “most likely” path determined. The identifying binary numbers of the final states of each file and the binary numbers of an original initial state determine the “most likely” sequence of convolutionally-encoded symbols received by the decoder. The convolutional decoding can be implemented with a digital signal processor and a dedicated peripheral unit. This apparatus can provide an efficient use of memory for the possible decoding paths.

Abstract: A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing a burst transfer include determining the starting address of the vector data to be transferred, the ending address of the vector data to be transferred, and whether the ending address of the vector data to be transferred is within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined based on the number of data elements to be transferred, the stride of the vector data to be transferred, and the width of the vector data elements to be transferred. When the amount of data to be transferred is divisible by a factor of two, the multiplication of the stride and width of the data elements is carried out by shifting.

Abstract: In a data processing system, the ability to provide indirect addressing capability is implemented by providing a peripheral system having a first memory unit, second memory unit, and a control unit. In a first embodiment of the invention, a first address signal applied to the control unit accesses a first location in the first memory unit. The signal group stored in the first location is a first address signal group. The first signal group is used by the control unit to access a second location in the second memory unit. The access of the second location can be used to store a data signal group therein in a write operation or can be used to retrieve a data signal group therefrom in a read operation. In the second embodiment of the invention, the control unit includes a pointer unit responsive to a plurality of control address signal groups. The control address signal groups cause the storage or retrieval of data signal groups in a data register in the control unit.

Abstract: An apparatus is disclosed for coating a semiconductor wafer with polyimide so that excess polyimide is removed from the wafer edge, back side and coating process area and is conveniently drained. A developer, such as dilute TMAH, that mixes with the excess polyimide is injected into a chamber. The soluble mixture of TMAH and excess polymide may then be drained into a bulk drain, obviating the accumulation of excess polymide in the coater cup. The method is implemented through an assembly that includes a coater cup, spin chuck disposed within the coater cup, and a pair of nozzles intruding into the coater cup at a lower portion of the cup. A fist nozzle operates to inject developing fluid onto the back side of the wafer in the cup, and a second nozzle, positioned nearer the center of the cup and the spin chuck, operates to inject rinsing fluid.

Abstract: An apparatus and method for implementing a decoder for convolutionally encoded symbols (e.g., a viterbi decoder) is described. In one embodiment, a file of all the initial states (or their equivalents) and the nth surviving states associated with the initial states is stored along with the path metric. The initial states (or their equivalents) are an index to a previous file. A new file or files are then generated. An appropriate criterion is utilized to select a final surviving state. The path can be traced back through a plurality of files and the “most likely” path determined. The identifying binary numbers of the final states of each file and the binary numbers of an original initial state determine the “most likely” sequence of convolutionally-encoded symbols received by the decoder.

Abstract: A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test pattern set from the change input and the initialization scan chain test pattern.

Abstract: A vector transfer unit for handling transfers of vector data between a memory and a data processor by one or more application programs in a computer system. A compiler identifies the use of vector data in the application program and implements one or more vector instructions for transferring the vector data between memory and registers used to perform calculations on the vector data. The compiler also schedules transfers of portions of the vector data required in a calculation so that calculations on a portion of the vector data are performed while a subsequent portion of the vector data is transferred. A vector buffer pool is partitioned into one or more vector buffers based on configuration information including the number of vectors buffers required by an application program and the size required for each vector buffer. The vector buffers are allocated for exclusive use by an application program that is executing in the data processor.

Abstract: A system for improving manufacture, said system including but not limited to a Polyimide solvent dispensing nozzle proximate to a Polyimide dispensing nozzle. In one embodiment, the Polyimide solvent dispensing nozzle proximate to a Polyimide dispensing nozzle further includes but is not limited to the Polyimide solvent dispensing nozzle coupled with a bracket assembly adjustable in three dimensions. In one embodiment, the Polyimide solvent dispensing nozzle coupled with a bracket assembly adjustable in three dimensions further includes but is not limited to a bracket assembly adjustable in an x-axis direction, y-axis direction, and z-axis direction. In one embodiment, the Polyimide solvent dispensing nozzle proximate to a Polyimide dispensing nozzle further includes but is not limited to the Polyimide solvent dispensing nozzle mounted on an arm holding the Polyimide dispensing nozzle.

Abstract: Provided is a test wafer and a process for making the same that includes a plurality of peaks on a surface thereof that have a cross-section sufficient to reduce the stress of a refractory metal layer deposited thereon. The present invention is based upon the discovery that by fracturing a refractory metal layer on a test wafer reduces the stress to which the test wafer is subjected. The test includes a substrate having a surface with a plurality of peaks and troughs formed therein defining a roughness. Typically, the roughness Ra is in the range of 500 to 1200 micrometers.