Abstract: A DRAM cell structure having a capacitance electrode with a tapered end surface is disclosed. Accordingly, the cell structure of this invention provides increased yield without increasing the number of process steps required to form the cell structure, A unique process for forming the capacitance electrode with a tapered end surface is also provided.

Abstract: A cache memory management unit that performs searches in a cache memory unit that supplements a disc memory that serves a digital computer. When the computer needs to write a chosen data block into, or read a chosen data block from, its disc memory, the unit first performs a search for the tag or identification label for the chosen data block in the cache memory unit, before the computer searches the disc memory. The unit also implements an algorithm that identifies the least recently used and most recently used cache data blocks.

Abstract: An N-word write access memory is described. Using a variation of conventional control signals RAS, CAS, WE and OE, an innovative scheme of signal protocol allows the N-bit word write memory to have an input/output bandwidth double that attained in the prior art, using substantially the same components and without affecting the bit-width, hence, the pin-count, of the external data bus.

Abstract: An architecture is provided for testing and emulating an integrated circuit with embedded function blocks. The output nodes of the function blocks are connected through a tri-state buffer to a test bus which in turn is connected to configurable external pins. The external pins multiplex the normal I/O in normal mode and the test bus I/O in the test mode. The test bus is also connected through multiplexers to input nodes of function blocks. In test mode, the function block nodes are accessed through the test bus. For emulation of an embedded microcontroller or microprocessor, the internal connections of the microcontroller (or microprocessor) are brought out to those external pins which in normal operation are connected only to the microcontroller and not to any other function block. An in-circuit emulator (ICE) emulating the microcontroller is connected to the other function blocks through those external pins.

Abstract: An asynchronous memory controller comprises plurality of flip-flops connected in a series. The input of the first flip-flop receives a signal indicating the start of a bus cycle. The input of each succeeding flip-flop in the series is connected to the output of the preceding flip-flop. The odd-numbered flip-flops in the series are activated by a first state of a clock pulse; the even-numbered flip-flops in the series are activated by a second state of a clock pulse. Each flip-flop responds to a level of the clock pulse rather than a rising or falling edge.

Abstract: In accordance with the present invention, a method of performing arithmetic division on a data flow machine is disclosed which resolves some of the inefficiencies associated with the conventional subtract until carry method. This method eliminates many of the numerous subtraction operations characterizing the conventional method by performing trial multiplications in the same way long hand division is performed. Furthermore, the method is implemented using data flow techniques to enhance the speed of the division by performing functions in parallel with a minimal memory requirement. As a result of this invention, integer division is performed using fewer clock cycles than a conventional Von Neuman implementation.

Abstract: A means for precisely identifying the location of an error in a computer program executing in a microprocessor is provided by an instruction complete counter circuit that counts each of the program instructions completed by the microprocessor up to the time of an error in execution.

Abstract: An improved ion source is provided with multiple filaments and wiring for selectively connecting various combinations of filaments to a current source. In one embodiment an additional filament is a spare filament which is connected to the current source when the primary filament burns out. This decreases down time due to filament replacement. In another embodiment, an additional filament operates simultaneously with a primary filament to provide a more homogenous electron cloud and to increase filament life.

Abstract: This invention discloses a tray for transporting Plastic Leaded Chip Carriers (PLCC's) which provides for secure alignment of a PLCC into an individual cavity of the tray and also holds the PLCC within the cavity so that the PLCC will not become misaligned. The invention accomplishes this without any contact with the leads of the PLCC thereby eliminating lead damage and minimizing the degradation of lead coplanarity. Furthermore, no modification of the PLCC is required.

Abstract: According to the principles of this invention, a polysilicon layer in a semiconductor device is shaped so that in subsequent processing steps a uniform topology is achieved. In particular, a first layer, typically polysilicon, is overlain by a second layer, typically spin-on glass, which is in turn overlain by a mask layer. An opening is formed in the mask layer and the second layer. An isotropic etchant is applied to the structure after the opening is formed. The etchant is formulated to have a differential etch rate in the first and the second layers so that the first layer after etching has an edge surface with a taper of less than 60.degree. and preferably about 45.degree..

Abstract: A method in which a variable sized segment of a memory array can be written in a single memory cycle is provided. A predetermined set of the column addresses or a combination of the column address and I/O field specify the starting location of a block of a memory array row to be written. The set of remaining column addresses specifies displacement from the starting location. Together the starting segment and the displacement define an area of memory which can be written in a single cycle.

Abstract: An apparatus is provided which determines whether a member is placed correctly on a base. The apparatus comprises an arm mounted for movement toward and away from the base which normally holds the member in place on the base. The arm has a projection which extends a distance beyond the surface of the arm and toward the base. When the member is in a first or third position relative to the base, the projection makes contact with the member. When the member is in a second position relative to the base, the projection clears the member and is positioned in close proximity to the side of the base. The apparatus determines the position of the member by sensing with a photosensor a corresponding position of the arm displaced from the base. The displacement distance of the arm relative to the base is due to the distance that the projection extends beyond the surface of the arm.

Abstract: A semiconductor memory cell with an N-type conductivity capacitance implant region self-aligned with a polysilicon transfer gate is disclosed. In a first embodiment after a blanket capacitance implant, formation of the capacitance storage polysilicon gate and an overlying insulating layer, a plasma etch is used to define specific regions of the capacitance implant. In a second embodiment, a complementary implant step is used after formation of the insulating layer over the capacitance storage polysilicon gate. Subsequently, in both embodiments, a transfer gate is formed with an edge surface adjacent to and abutting the insulating layer over the capacitance storage gate and substantially aligned with an edge surface of the capacitance implant region.

Abstract: A FET transistor has a gate structure consisting of at least three layers of polysilicon with a thin oxide layer on the order of atoms thick separating each of the layers. A method for formation of the multilayer gate structure and the formation of resistors comprised of layers of polysilicon separated by oxide layers are also provided.

Abstract: An apparatus is described which controls the movement and positioning of a platen on which wafers may be mounted. The apparatus comprises a stepper motor having a motor sprocket member operatively coupled to a platen by a drive mechanism. The drive mechanism comprises a chain which cooperates with the the stepper motor by engaging with the motor sprocket member. The drive mechanism also comprises a platen chain sprocket having a platen shaft member. The platen is movably connected to the platen shaft member. The chain cooperates with the platen by engaging with the platen chain sprocket. Operation of the stepper motor rotates the motor sprocket member and drives the drive mechanism, thereby rotating the platen chain sprocket and determining the movement and positioning of the platen. The apparatus is capable of controlled movement and positioning of the platen inside processing equipment, such as ion implantation equipment.

Abstract: A DRAM cell structure having a capacitance electrode with a tapered end surface is disclosed. The tapered end surface eliminates prior art structures formed during fabrication of the cell structure that decreased yield. The cell structure of this invention provides increased yield without increasing the number of process steps required to form the cell structure. A unique process for forming the capacitance electrode with a tapered end surface is also provided.

Abstract: A mini-relay signal tester designed to simplify, speed up, and test the operation of "mini" or "reed" relays which are suspected of intermittent failure. These types of relays are extensively used in memory and gate-array testing systems and their failure can cause the semiconductor devices being tested to be erroneously rejected. The relay tester dynamically exercises the relay being tested by application of a square-wave input signal to its coil. The square wave input "reference" signal driving the relay coil is then compared to a square wave output "test" signal which is generated by the contacts of the relay being tested. The signals are compared on a dual-trace oscilloscope. When difference between signals exceeds acceptable standards the relay is rejected.

Abstract: A leak and liquid level detector includes a transistor as its main operating element with a pair of normally open base contacts connected to the transistor base. The transistor emitter is connected to ground and the transistor collector is connected to a suitable audio alarm, or alarm light or to a programmable logic controller. When a liquid leak bridges over the base contacts, a power circuit is closed across the contacts biasing the transistor and causing an electrical signal to flow from the collector to actuate the alarm, light or controller. The base contacts are linearly adjustable to sense various leak heights. The detector in one mode of use can be positioned horizontally to detect leaks and in a second mode of use is positioned vertically to detect a change in a liquid level in a tank, pipe column or the like.

Abstract: A dual input universal logic structure allows many logical functions to be implemented using a relatively small number of CMOS transistors. The dual input structure implements the following logical equation:OUT=A+BorOUT=A.multidot.B.The dual input universal logic structure comprises a p-channel field-effect transistor (FET) and an N-channel field-effect transistor. A multiplexer circuit and an exclusive NOR circuit which each require only four CMOS transistors may be implemented using the dual input logic structure. likewise, a two-by-four decoder may be implemented using only ten CMOS transistors. Since a fewer number of CMOS transistors are required to implement certain functions, the space requirements of the circuits are reduced and denser circuit packaging may be achieved in VLSI integrated circuits. In addition, the dual input logic structure may be used within a random access memory circuit to decrease power consumption and soft error rate.

Abstract: A stepper motor control circuit having a reduced number of discrete components is provided by using an on-chip analog to digital converter of a single chip microcomputer to control the waveforms of chopped winding currents. Four power MOSFET's, four diodes and two sense resistors can be added to the circuitry of a board populated by the single chip microcomputer to implement a full step motor controller. The addition of a holding current circuit frees the computer for servicing other tasks when the motor is idle.