Abstract: A fault-tolerant management information system includes three or more data management systems (e.g. data base systems) that replicate data. Data access requests resulting from user requests to application systems are issued by user request processing entities and forwarded by interceptors to all the data management systems. Responses from the data management systems are obtained, and a maximum group of identical responses provides the correct response, even in the case of "soft" errors not flagged by error codes. Errors are reported to an administration system, and correction of the data base containing the errors is handled by a recovery server. Overall system performance is further enhanced by including data base query systems, which replicate the data. Data access requests resulting from data base query requests are issued by query systems to the data base query systems.

Abstract: Analog-to-digital (ADC) output bits are partitioned in a way that simplifies the gain error calculations. Simplification of the gain error calculations allows a reduction in the complexity of the circuits needed to implement automatic gain control (AGC).

Abstract: A manufacturing system is disclosed which includes first and second control devices as well as a communication terminal which controls communication with the control devices. The communications terminal includes an interceptor module which receives information from the manufacturing device and provides this information to the first and second control devices.

Abstract: Interleaved operation of multiple memory banks is improved by including a frequency multiplier and a synchronizing circuit, such as a phase-locked loop, as part of an integrated circuit memory chip. Frequency multiplication supplies additional clock edges for timing different phases of the system clock signal. The synchronizing circuit provide precise control of clock edge timing to exactly align the timing signals in one memory chip with the timing signals in another memory chip despite variability in temperature, process and voltage parameters between the chips.

Abstract: An image compression system has an image memory accessible from the image bus. Compressed data are stored in a dual-ported memory accessible from both the image bus and the host bus. The compressor/expander accesses the image memory while the host accesses the dual-ported memory. Dual-ported memory allocation schemes and a computer program controlling the image compression system are also provided.

Abstract: A spincup having a wafer backside deposition reduction apparatus is used to reduce wafer backside particle deposition of materials on a wafer during processing. The spincup includes an opening for accommodating a wafer supporting chuck and a particle guard which circumscribes the chuck. The particle guard contacts the base of the spincup and circumscribes the chuck. When the chuck supports a wafer, a wafer backside region is defined between the chuck and the particle guard. The spincup further includes an exhaust channel coupled to the wafer backside region to independently exhaust the wafer backside region. In one embodiment, the exhaust channel includes an exhaust port for connecting a vacuum generator to the exhaust channel and a shroud contacting a base of the spincup and the particle guard. In another embodiment, the exhaust channel includes exhaust tubes which replace the exhaust manifold shroud and exhaust port.

Abstract: A supplemental monitoring device which issues an error signal when the monitoring device loses motor drive pulses is disclosed. Also disclosed is providing a manufacturing system with a normally closed relay which controls the flag, thus advantageously providing a semiconductor system which automatically interrupts the ion beam in the event of a system malfunction.

Abstract: Methods are provided for generating a square wave of variable duty cycle using a microprocessor and an interval timer. The duty cycle can be changed without changing the period. The duty cycle is changed on a rising or a falling edge of the signal as desired.

Abstract: A test system 100 for performing electrical testing in a high voltage or inhospitable or inconvenient environment 150 electrically isolates a measurement detector 130 located within the environment from an externally located measurement result display and selector 110. Electrical isolation is accomplished using a non-conducting fiber optic link 120 for communicating the measurement results.

Abstract: A current switch for high-speed and high-resolution digital to analog converters (DACs) employs MOSFET devices to control the current switch output in response to binary input signals at logic level voltages. The current switch reduces ringing of the output current that occurs when switching takes place to improve DAC high speed performance by protecting current steering MOSFET transistors against application of the full swing voltage of the binary input signal by applying lower voltage switching signals in place of the full swing logic level voltages. Furthermore, the current switch compensates for parasitic capacitances within the current steering MOSFET transistor that drives the output current.

Abstract: A discrete cosine transform engine is disclosed. The engine receives an input matrix of data and provides a transformed matrix of data, the input matrix and the output matrix each having a plurality of row locations and a plurality of column locations. The engine includes a plurality of input accumulators and a plurality of output accumulators. The plurality of input accumulators accumulate data from the input matrix of data in parallel to provide a plurality of transform coefficient outputs. A digital signal processor receives the plurality of transform coefficients, multiplies the transform coefficients by a plurality of transform constants and provides a plurality of transform products. Each output accumulator receives the transform products and accumulates the products to provide the transformed matrix of data.

Abstract: Cache memory input/output apparatus that allows transfer of a single data word and transfer of consecutive sequences of data words in a row of memory, using two independent serial ports and a random access port whose actions are controlled in part by a memory address signal. Data transferred by the serial ports are double buffered, each serial port having two independent registers; and the two registers associated with a serial port may be ganged together to transfer data sequences having word lengths from 16, or multiples thereof, up to arbitrary multiples of the length of a row of data words.

Abstract: An improved ion source is provided with multiple filaments and wiring for selectively connecting various combinations of filaments to a current source. In one embodiment an additional filament is a spare filament which is connected to the current source when the primary filament burns out. This decreases down time due to filament replacement. In another embodiment, an additional filament operates simultaneously with a primary filament to provide a more homogenous electron cloud and to increase filament life.

Abstract: A Forward Feed Neural Network is disclosed using data flow techniques on a data flow microprocessor. As a result of this invention, a neural network is provided that has the capacity of "learning" to distinguish among patterns of data which may differ recognizably from idealized cases, and is able to perform pattern recognition faster while utilizing less memory and fewer clock cycles than neural networks implemented on sequential processors. This implementation is simpler and faster because of an inherent similarity between the flow of information in the brain and in data flow architecture.

Abstract: A discrete cosine transform engine which receives an input matrix of data and provides a transformed matrix of data, the input matrix and the output matrix each having a plurality of row locations and a plurality of column locations. The engine includes a plurality of input accumulators, a plurality of multiplication circuits and a plurality of output accumulators. The plurality of accumulators accumulate data from the input matrix of data in parallel to provide a plurality of transform coefficient outputs. The plurality of multiplication circuits receive the plurality of coefficient outputs and multiply the coefficient outputs by transform constants to provide a plurality of transform products. Each output accumulator receives the transform products and accumulates the products to provide the transformed matrix of data.

Abstract: A solvent fume exhaust scrubber (100) for recovering organic vapor from exhaust air which is produced during the manufacture of semiconductors includes a throttling chamber (180) containing a plurality of planar baffles (112, 114, 116, 118 and 120), a planar condenser (130) and a cooling coil (138) which engages and substantially traverses the planar surface of the condenser. The throttling chamber intersects an exhaust duct (152) so that an exhaust stream (182) flows in a flow direction (184) through the chamber. Each baffle and condenser has a planar surface which is disposed at right angles to the flow direction. The surface extends partially across the exhaust stream. The baffles are arranged sequentially along the flow direction and have offsetting planar surfaces across the exhaust stream so that the baffles in combination extend across the exhaust stream. A baffle includes a baffle frame (302) for holding a plurality of carbon beads (306).

Abstract: A programmable digital circuit is provided for bus control of a fast microprocessor such as a V33 microprocessor. The digital circuit includes a bus controller, a wait state controller and a clock generator generating a processor clock and a system clock with but a small skew between them.

Abstract: An image compression system has an image memory accessible from the image bus. Compressed data are stored in a dual-ported memory accessible from both the image bus and the host bus. The compressor/expander accesses the image memory while the host accesses the dual-ported memory. Dual-ported memory allocation schemes and a computer program controlling the image compression system are also provided.

Abstract: Methods are provided for generating a square wave of variable duty cycle using a microprocessor and an interval timer. The duty cycle can be changed without changing the period. The duty cycle is changed on a rising or a falling edge of the signal as desired.

Abstract: A current switch for high-speed and high-resolution digital to analog converters (DACs) employs MOSFET devices to control the current switch output in response to binary input signals at logic level voltages. The current switch reduces ringing of the output current that occurs when switching takes place to improve DAC high speed performance by protecting current steering MOSFET transistors against application of the full swing voltage of the binary input signal by applying lower voltage switching signals in place of the full swing logic level voltages. Furthermore, the current switch compensates for parasitic capacitances within the current steering MOSFET transistor that drives the output current.