Abstract: A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing a burst transfer include determining the starting address of the vector data to be transferred, the ending address of the vector data to be transferred, and whether the ending address of the vector data to be transferred is within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined based on the number of data elements to be transferred, the stride of the vector data to be transferred, and the width of the vector data elements to be transferred. When the amount of data to be transferred is divisible by a factor of two, the multiplication of the stride and width of the data elements is carried out by shifting.

Abstract: A method correlates a timing target for electronic design automation (EDA) design tools by comparing slack distributions. A method of designing an integrated circuit can include designing an integrated circuit by RTL synthesis with embedded timing analysis and optimization and placement of cells with embedded timing analysis and optimization. The method can also include designing an integrated circuit by routing with embedded timing analysis and optimization; performing reference timing analysis; performing reference timing analysis and embedded timing analysis using a parasitic estimation model. The method can also include comparing at least two slack distributions resulting from timing analyses. The method can include calculating and comparing autocorrelation functions of slack distributions. The method can include calculating interrcorrelation functions of slack distributions. An embodiment teaches an integrated circuit designed by the method taught.

Abstract: A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test pattern set from the change input and the initialization scan chain test pattern.

Abstract: A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.

Abstract: A method and system for use in wafer fabrication systems. The method and system capture an evolving wafer fabrication system by mapping at least one interaction between a selected at least one integral part associated with the wafer fabrication system and at least one other integral part associated with the wafer fabrication system.

Abstract: A data processing system for use in arrays includes a digital signal processor, a search accelerator unit and memory unit, the memory unit having a group storage locations that store the data entries of the matrix. The locations in the matrix are identified by the indices of the location. The access of the matrix by the digital processing unit typically includes an access to a series of locations at periodic intervals along a row or diagonal of the matrix. The series of data entries can include a sequence of non-neighboring matrix data entries. The search accelerator unit includes at least one pointer unit. The pointer unit in the search accelerator unit receives beginning array indices identifying the array entry. The pointer unit increments the array indices to provide the sequence of data entry indices for the matrix. The data entry array indices are converted to a series of memory location addresses.

Abstract: A voltage reference generating circuit for providing voltage references substantially less than the typical 1300 mV, with a controllable thermal coefficient. By forcing equal-valued currents through two semiconductor junctions having disparate junction areas, a voltage differential is developed, as is a current proportional to the voltage differential. The voltage differential, and a current proportional to the voltage differential, have positive thermal coefficients. A third semiconductor junction is biased from a third current source and bridged by a resistor pair so as to synthesize a Thevenin-equivalent voltage equivalent series resistance. The equivalent voltage has a negative thermal coefficient. By forcing a current that is equal to the proportional current through the equivalent resistance, a reference voltage, equal to the sum of the Thevenin-equivalent voltage plus the voltage drop across the Thevenin-equivalent resistance, is created.

Abstract: A method and circuit for allowing direct access logic testing in integrated circuits. In one embodiment, an interface between integrated circuit core logic and integrated circuit user-defined logic is exposed, and the integrated circuit core logic and the integrated circuit user-defined logic is tested via the exposed interface. In another embodiment, an integrated circuit has logic selection circuitry connected with core logic and user-defined logic. The logic selection circuitry is used to selectively test the core logic and user-defined logic.

Abstract: When a processing unit clock cycle period decreases (i.e., the processing unit operating frequency increases) such that the processing unit has only sufficient time to transfer accurately instruction fields from the instruction cache unit, the processing unit does not have sufficient time to determine the address of the next instruction to be retrieved from the instruction cache unit. In order to provide instruction fields to a pipelined processing unit with few breaks in the instruction field stream, the field in the program counter is incremented during to provide a speculative address of a next instruction field during a first clock cycle. During the first clock cycle, the instruction field identified by program counter field is accessed and transferred to the processor. The instruction field helps to determine an actual address of the next instruction field.

Abstract: A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include, interfaces, cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is independently addressable, such that particular memory masters can be assigned to access particular virtual access channels.

Abstract: A manufacturing system is disclosed which includes first and second control devices as well as a communication terminal which controls communication with the control devices. The communications terminal includes an interceptor module which receives information from the manufacturing device and provides this information to the first and second control devices.

Abstract: A method for use in forming a capacitor having a hollow-cylinder electrode structure in a semiconductor device via controlled reactive etching of substantially only one semiconducting layer of a semiconductor device. In one embodiment, the device is a dynamic random access memory (DRAM) structure. In another embodiment, the device is a microprocessor.

Abstract: In a semiconductor device fabrication process, a method of, and apparatus for, coating a semiconductor wafer with polyimide so that excess polyimide is removed from the wafer edge, back side and coating process area and is conveniently drained. The method comprises the injection into the chamber of a developer, such as dilute TMAH, that mixes with the excess polyimide. The soluble mixture of TMAH and excess polyimide may then be drained into a bulk drain, obviating the accumulation of excess polyimide in the coater cup. The method is implemented through an assembly that includes a coater cup, spin chuck disposed within the coater cup, and a pair of nozzles intruding into the coater cup at a lower portion of the cup. A fist nozzle operates to inject developing fluid onto the back side of the wafer in the cup, and a second nozzle, positioned nearer the center of the cup and the spin chuck, operates to inject rinsing fluid.

Abstract: A device that broadcasts an electronic serial number, or ESN, is made secure from cloning using one or more of a plurality of measures, including coupling the memory used for storing the ESN more closely to the ESN processor, fabricating the ESN memory as part of the ESN processor, including the ESN memory in another processor and encrypting communications between the other processor and the ESN processor, and comparing multiple copies of the ESN stored in different memories. The later technique is also effective in securing the JTAG port of an ESN processor.

Abstract: A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.

Abstract: Apparatus and methods are disclosed for adaptively optimizing an ER filter in a readback system of a storage device, such as a disk drive. A sample value is read from the storage device and an error measure is calculated between the sample value and an ideal value. Pole parameters and zeros of the ER filter are modified to minimize the ER filter. The apparatus and methods disclosed can function with customer data to adaptively optimize the ER filter in real time during normal operation of the storage device. Furthermore, temperature compensation circuits are disclosed to compensate for temperature dependencies in the ER filter.

Abstract: A bit field system is disclosed which includes a processor as well as a bit field peripheral device which is accessed via dedicated bit field addresses. Such a system efficiently executes bit field operations. Additionally, such a system advantageously provides a processor which does not include an original bit field instruction set with the ability of performing bit field operations. Such a system also advantageously avoids difficulties involved in encoding bit field instructions.

Abstract: Apparatus and Methods are disclosed for adaptively optimizing an ER filter in a readback system of a storage device, such as a disk drive. A sample value is read from the storage device and an error measure is calculated between the sample value and an ideal value. Pole parameters and zeros of the ER filter are modified to minimize the ER filter. The apparatus and methods disclosed can function with customer data to adaptively optimize the ER filter in real time during normal operation of the storage device. Furthermore, temperature compensation circuits are disclosed to compensate for temperature dependencies in the ER filter.

Abstract: A less complex maximum likelihood detector can be implemented in a partial response maximum likelihood (PRML) system without degrading system performance by saturating y values from a gain control loop to a smaller range before the y values are supplied to the maximum likelihood detector. A quantity "D" of a maximum likelihood detector operating in accordance with a partial response scheme has a particular relationship with respect to the maximum (ymax) of the y input values processed by the maximum likelihood detector. In some embodiments, y values from a gain control loop are saturated from a first larger range (defined by ymaxreal) to a second smaller range (defined by a value SAT) which is at least as great as the ymax of the ideal input signal (ymaxideal) for the partial response scheme. The saturated y values are provided to the maximum likelihood detector.

Abstract: A computer system having a processor and at least one peripheral has a programmable shared memory system and method that selectively dedicates a first potion of memory to use by the processor and allocates a second portion of memory to shared use by the processor and any peripherals in the system. The programmable memory architecture is implemented using a dual bus architecture having a first-bus connected to the processor and a second bus coupled to the processor by a system controller and to the peripherals by a peripheral controller. The programmable memory architecture additionally has a configuration controller coupled to each configurable memory bank in the system. Each configuration controller is additionally coupled to both the first and second buses. Under programmed control, the each configuration controller couples the associated memory to either the first or second bus, responsive to configuration information stored in the system controller.