Patents Assigned to NEC Electronics
  • Patent number: 7605736
    Abstract: An A/D converter comprises a sample and hold circuit receiving a signal and operating based on a sampling clock, an A/D converting circuit converting an output signal of the sample and hold circuit to a digital signal, an A/D output determination circuit outputting a duty control signal based on the digital signal and a sampling clock generator adjusting a duty ratio of a sampling clock and applying the sampling clock to the sample and hold circuit.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: October 20, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Hidemi Noguchi
  • Patent number: 7607074
    Abstract: An error detector includes a substitute value output section outputting a specific substitute value corresponding to an encoding byte sequence Q of input byte data by referring to a table storing, as a substitute value, a value obtained by inputting a substitute code string to a shift register that produces an error detecting value upon input of a code string in an encoding byte sequence Q, a bit processing operation section calculating an error detecting value per byte, and a byte processing operation section outputting an error detecting value of a code string. The substitute code string contains byte data of K number of bytes where only predetermined bit data in byte data corresponding to the encoding byte sequence Q indicates “1” and all other bit data indicates “0”. The bit processing operation section processes each byte data and its substitute value in a different processing sequence from the encoding sequence.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: October 20, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Hiroki Takeuchi
  • Publication number: 20090255389
    Abstract: There is provided a lead cutter that enables micro-adjusting a cutting clearance between a punch and a die with high accuracy. The lead cutter includes a die on which the lead provided in an encapsulating resin enclosing a semiconductor chip is to be placed, a punch that vertically moves relative to the die to thereby cut the lead, and a temperature controller that controls a temperature of at least one of the punch and the die, so as to adjust a clearance between the punch and the die.
    Type: Application
    Filed: March 23, 2009
    Publication date: October 15, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Tooru Kumamoto
  • Publication number: 20090259902
    Abstract: Provided is a semiconductor device that can be reduced in size while variation in shape among circuit patterns is reduced. The semiconductor device includes multiple circuit patterns and first dummy patterns. The multiple circuit patterns are disposed at regular intervals, and are used as part of the circuit. The multiple circuit patterns consist of two outermost circuit patterns and the other inner circuit patterns. The first dummy patterns are disposed on outer sides of the two outermost circuit patterns, respectively. The distance between each of the outermost circuit patterns and the corresponding first dummy pattern is equal to a distance between any adjacent two of the circuit patterns. A width of each of the first dummy patterns is smaller than a width of any of the circuit patterns, and is equal to a minimum design rule width, for example.
    Type: Application
    Filed: March 20, 2009
    Publication date: October 15, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Takashi Tahata
  • Publication number: 20090256493
    Abstract: A driving circuit, which drives a display panel in a voltage range between a high negative voltage and a high positive voltage, includes: an electric charge discharging circuit; and a test external terminal. The electric charge discharging circuit connects a first terminal supplied with the high negative voltage to a second terminal of a ground voltage in response to a drop of a power source voltage. The test external terminal is connected to the electric charge discharging circuit. The high negative voltage is supplied to the semiconductor substrate. The electric charge discharging circuit interrupts a connection between the first terminal and the second terminal based on a control signal from the test external terminal.
    Type: Application
    Filed: March 24, 2009
    Publication date: October 15, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Fumio Tonomura
  • Patent number: 7603489
    Abstract: DMAC includes current transfer setting registers and next transfer setting registers. Each of the current transfer setting registers stores transfer source address, transfer destination address and transfer count. The next transfer setting registers stores a transfer setting of a DMA transfer carried out after completing a DMA transfer according to a current transfer setting stored in the current transfer setting registers as a next transfer setting. Further, flags are provided for controlling to write to each of the next transfer setting registers.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Toru Ikeuchi
  • Patent number: 7602875
    Abstract: A sampling apparatus for converting first data, sampled at a first sampling rate, into second data, sampled at a second sampling rate. A FIFO storing the first data based on a write control signal and outputs the second data read out based on a read control signal indicating whether the second data is to be read out during the next time interval. The apparatus further includes a frequency detection unit for measuring the first clock signal during the current time interval to generate the value of the first current clock frequency, generating the value of a current predicted clock frequency from the value of the first current clock frequency and the value of the directly previously predicted clock frequency and for using the value of the current predicted clock frequency as the directly previously predicted clock frequency during the next time interval.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Eiji Sudo, Yasushi Ooi
  • Patent number: 7601640
    Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
  • Patent number: 7603595
    Abstract: A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and including a plurality of test actions for the memory, and stores the pattern mode signal as failure information in a failure information storage register. The circuit includes a storage determining circuit determining whether or not to store the failure information in a failure information storage register based on preset failure information storage method information.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Tomonori Sasaki
  • Patent number: 7602048
    Abstract: The object of the present invention is to improve the interfacial adhesion between the film with low dielectric constant and protective film, without damaging the excellent dielectric, flatness and gap-filling characteristics of the organic material of low dielectric constant, and for that purpose there is provided a wiring structure with the copper film embedded in the insulation film of the wiring layer, wherein the insulation film of the wiring layer is of a multi-layered structure with the laminated methyl silsesquioxane (MSQ) film, methylated hydrogen silsesquioxane (MHSQ) film and silicon oxide film.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Tatsuya Usami
  • Patent number: 7603579
    Abstract: A semiconductor chip has: a plurality of hard macros which operates based on a reference clock; and a clock pad through which the reference clock is supplied from the outside to one of the plurality of hard macros. The reference clock supplied to the one hard macro is relayed to other hard macros of the plurality of hard macros in order.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Nobuo Furuya
  • Patent number: 7602002
    Abstract: The present invention provides a semiconductor device comprising: a semiconductor substrate having a DRAM portion and a Logic portion; a first transistor in said DRAM portion; a second transistor in said Logic portion; a first insulating layer covering said DRAM portion and said Logic portion; a first contact plug formed in said first insulating layer in electrically contact with said first transistor in said DRAM portion; a first bit line for said DRAM portion formed on said first insulating layer in electrically contact with said first contact plug; a nitride film formed in contact with said first insulating layer to cover said DRAM portion and said Logic portion, wherein said first bit line locating between said first insulating layer and said nitride film.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Tomoko Inoue, Ken Inoue
  • Patent number: 7602064
    Abstract: The semiconductor device includes a semiconductor substrate, a diffusion layer, an interconnect layer, a contact plug, a contact-inspection hole, a via plug, and a via-inspection hole. Similarly to a contact plug hole, the contact-inspection hole extends from the diffusion layer to the interconnect layer. The opening of the contact-inspection hole on the side of the diffusion layer is disposed across the boundary of the diffusion layer. Also, similarly to a via plug hole, the via-inspection hole extends from an interconnect to an interconnect layer. The opening of the via-inspection hole on the side of the interconnect is disposed across the boundary of the interconnect.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Masatoshi Watarai, Ryuichi Okamura
  • Patent number: 7602058
    Abstract: A semiconductor device is composed of a power supply interconnection extending from a certain starting point in a first direction and also extending from the starting point in a second direction orthogonal to the first direction, a plurality of power pads, and connecting interconnections providing electrical connection between the power supply interconnection and the power pads. The power supply interconnection, the power pads, and the connecting interconnections are arranged in a symmetrical manner with respect to a symmetry line crossing the starting point and extending in a direction at an angle of 45 degree to the first and second directions.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Toshikazu Katou
  • Patent number: 7602827
    Abstract: There is provided a semiconductor laser comprising an n-InP substrate 1; a multilayer film including a strained MQW active layer 6 on the n-InP substrate 1; a p-electrode 18 on the multilayer film; a pair of grooves 15 separating the multilayer film in both edges of the p-electrode 18 and extending to the n-InP substrate 1; and a plurality of diffraction gratings formed in an area from one to the other of the pair of grooves 15 in a diffraction grating forming surface formed in the upper surface of the n-InP substrate 1 or the upper surface of any of the semiconductor films in the multilayer film.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Tetsuro Okuda
  • Patent number: 7603510
    Abstract: A semiconductor storage device including a first latch circuit for latching stored data and a storage cell part including a plurality of second latch circuits that operate with inverted logic from the first latch circuit and receives the stored data from the first latch circuit to output the received data using the second latch circuit selected in accordance with a selection signal.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Satoshi Chiba
  • Patent number: 7602018
    Abstract: A high withstand-voltage semiconductor device has a gate electrode in a semiconductor layer of one conductivity type, a drain diffusion layer and a source diffusion layer, a thick gate insulating layer between the drain diffusion layer and the gate electrode, and a low-concentration offset diffusion layer of the opposite conductivity type in a region including the drain diffusion layer. A buried layer of the one conductivity type, which has a higher concentration than the semiconductor layer, is provided directly under the gate electrode at approximately the same depth as the depth of the offset diffusion layer. The buried layer disperses field concentration at the drain junction to thereby ensure a higher withstand voltage.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Takeshi Iida
  • Publication number: 20090250809
    Abstract: A semiconductor package includes a package-substrate, a first cavity formed on a first main surface of the package substrate, a first semiconductor chip mounted on the bottom surface of the first cavity, a first resin layer filled into the first cavity, and a thermal stress canceller member mounted on the package substrate for cancelling the thermal stress caused by the difference in the thermal expansion rates between the package substrate and mounting section including a first semiconductor chip and a first resin layer. The thermal stress canceller member may include a second cavity, a second resin layer filled into the second cavity, and a semiconductor chip.
    Type: Application
    Filed: March 19, 2009
    Publication date: October 8, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Yuichi Yoshida
  • Publication number: 20090251275
    Abstract: A semiconductor device 1 has a semiconductor substrate and a first electrical fuse 12 and a second electrical fuse 13, which are provided on the semiconductor substrate. The first electrical fuse 12 has a first upper layer wire 121 and a first lower layer wire 122 formed in different wire layers, and a via 123 for connecting the first upper layer wire 121 to the first lower layer wire 122. The second electrical fuse 13 has a second upper layer wire 131 and a second lower layer wire 132 formed in different wire layers, and a via 133 for connecting the second upper layer wire 131 to the second lower layer wire 132. The semiconductor device 1 has a connection portion 14 for connecting the above described first upper layer wire 121 of the first electrical fuse 12 to the second lower layer wire 132 of the second electrical fuse 13. The connection portion 14 connects the first electrical fuse 12 and the second electrical fuse 13 in series.
    Type: Application
    Filed: March 20, 2009
    Publication date: October 8, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Hiroshi Tsuda
  • Publication number: 20090250826
    Abstract: A process for manufacturing a semiconductor device that inhibits deterioration in the quality of the semiconductor device and a semiconductor device manufactured on such manufacturing process are presented. An operation of determining time-variation of water content in the resin substrate 11 (processing S1); an operation of coupling the semiconductor element 12 onto the resin substrate 11 through a plurality of electroconductive bumps B (processing S3); a first heating operation for controlling a water content of the resin substrate 11 to equal to or lower than 0.02% by heating said resin substrate and said semiconductor element while maintaining the coupling through said bumps (processing S6); and a first heating operation for controlling a water content of the resin substrate 11 to equal to or lower than 0.
    Type: Application
    Filed: March 18, 2009
    Publication date: October 8, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Teruji Inomata