Abstract: In a triangular-wave generating apparatus including an output terminal adapted to output an output voltage, an incorporated capacitor connected to the output terminal, a first variable current source adapted to charge the incorporated capacitor and a second variable current source adapted to discharge the incorporated capacitor, a charging/discharging current setting circuit sets a charging current in the first variable current source and sets a discharging current in the second variable current source. A level determining circuit determines whether or not the output voltage reaches one of predetermined voltages, to generate timing signals. A reference clock signal generating circuit generates a reference clock signal for defining a frequency of the output voltage. A charging/discharging current adjusting circuit adjusts the charging current and the discharging current in accordance with the timing signals and the reference clock signal.

Abstract: In a semiconductor device, a metal oxide semiconductor field effect transistor (MOSFET) is formed in a semiconductor substrate, and an isolation layer is formed on the semiconductor substrate so as to extend along a side of the semiconductor substrate. A first conductive layer is formed on the isolation layer along the side of the semiconductor substrate so as to be electrically connected to a gate of the MOSFET. A second conductive layer is formed on the isolation layer along the side of the semiconductor substrate so as to be electrically connected to a drain of the MOSFET. A protection circuit is made of at least two diodes which are defined between the first conductive layer and the second conductive layer.

Abstract: An inverting negative voltage DC-DC power supply circuit comprises a first resistor having one end connected to an output terminal for converting a change in output voltage into a current. A zero-volt clamp circuit is connected to the other end of the first resistor and comprises a first and second transistor. A current mirror circuit comprises a third and fourth transistor and is connected to the zero-volt clamp circuit for causing a current of the same value as that of a current flowing in the zero-volt clamp circuit to flow. A second resistor is connected to the current mirror circuit for converting a change in current flowing from the zero-volt clamp circuit into a voltage.

Abstract: Obtained is a highly-reliable non-volatile memory without increasing the area of a memory cell or adding a step to a CMOS process. The non-volatile memory includes an SRAM cell configured of 6 MOS transistors, a first word line electrically connected to the gate of a first transfer MOS transistor, and a second word line electrically connected to the gate of a second transfer MOS transistor. During a write operation of a first PMOS transistor, a drive circuit applies a positive voltage whose absolute value is not larger than a junction breakdown voltage to an n-type well as well as the sources of first and second PMOS transistors, concurrently applying the positive voltage to the first word line and a ground voltage to the second word line and a first data line.

Abstract: To provide a multi-processing system capable of continuing an operation with efficiency even if a failure occurs in a processor during a system operation. A multi-processing system according to an embodiment of the invention includes: a memory storing a program and information necessary for executing the program; a processor manager reading the program from the memory, dividing the read program into threads with priority, and assigning the threads to at least two processors based on the priority of the threads and a processing state of each processor; the at least two processors executing the threads assigned by the processor manager; and a processing data manager storing information necessary for executing the thread assigned by the processor manager, and outputting the stored information necessary for executing the assigned thread to the memory if a failure occurs in one of the processors.

Abstract: In a power supply control apparatus for controlling supplying of power from a battery to a load including a battery terminal connectable to the battery, an output terminal connectable to the load, and a ground terminal, a transistor is connected between the battery terminal and the output terminal to turn ON and OFF a connection between the battery and the load. An overcurrent detecting circuit is connected between the battery terminal and the output terminal to detect whether or not an overcurrent has flown through the transistor. A control circuit is connected between the battery terminal and the ground terminal to activate the transistor and the overcurrent detecting circuit.

Abstract: A data processing system is provided which includes a plurality of components to perform prescribed processing based on an operation mode, a chain controller to perform control including setting of the operation mode on at least one of the plurality of components, a storage unit to store chain configuration definition information associating at least one of the plurality of components with the chain controller for each prescribed data processing, and a configuration management unit to receive a processing request for the prescribed data processing and form a chain corresponding to the requested data processing based on the chain configuration definition information.

Abstract: Provided is a semiconductor device including a first region, a source region, a second region, a drain region, a gate insulating layer, a field insulating layer and a gate electrode. The first region is formed in a surface area of a semiconductor substrate. The source region is formed in a surface area of the first region. The second region is formed in a surface area of the semiconductor substrate. The drain region is formed in a surface region of the second region. The gate insulating layer is formed on a front surface of the semiconductor substrate between the source region and the second region. The field insulating layer is formed in a surface area of the semiconductor substrate between the drain region and the gate insulating layer. The gate electrode covers part of the gate insulating layer and part of the field insulating layer.

Abstract: An automatic updating apparatus includes a start instructing unit that outputs an analysis start signal at given intervals, an access count analysis unit that calculates an access count for each of menus indicated in a menu list on a network in response to the analysis start signal, calculates predictive evaluated values based on a variation in the access count within a unit time for each of the menus indicated in the menu list, and outputs a start signal unless the predictive evaluated values are arranged in order of a magnitude relation, and a menu updating unit that acquires the predictive evaluated values according to the start signal, and updates contents of the menus indicated in the menu list according to respective magnitude relations of the predictive evaluated values.

Abstract: A solid-state imager including an imaging region, a color filter layer, and an electro-conductive component, wherein the imaging region has a plurality of light receiving elements positioned therein, the plurality of light receiving elements are formed to a substrate, while being arranged in a two-dimensional manner, the color filter layer is formed over and around the imaging region, the electro-conductive component exposes from the color filter layer, the electro-conductive component is positioned around the imaging region but without overlapping the imaging region.

Abstract: A differential amplifier circuit includes an offset adjuster circuit for varying the active load to adjust the offset caused by the differential pair. The differential amplifier circuit includes fine adjustment cell sections including a plurality of transistors having the substantially same size, and shift cell sections including transistors, whose transistor size is larger than the transistors of the fine adjustment cell sections.

Abstract: A method of manufacturing a semiconductor device capable of obtaining high joining force between a heat spreader and resin is provided. The method of manufacturing a semiconductor device according to the present invention includes: setting a heat spreader 60 on a face formed a plurality of apertures 22 in a cavity 21 of a first molding die 14; filling resin 20 into the cavity; setting a substrate 54 mounted with a semiconductor chip 50 a second molding die 12; and pressure-welding the first molding die 14 and the second molding die 12 so that the semiconductor chip is embedded in the resin 20, wherein a plurality of concave portion is formed on one face of the heat spreader 60, a plurality of convex portions is formed on the other face of the heat spreader 60, and the plurality of concave portions and the plurality of convex portions are overlapped in plan view.

Abstract: A mobile terminal 1 includes a power measurement part which measures a received power of a radio signal received from outside, a movement estimator which estimates a moving state of the mobile terminal from an information included in the radio signal, and a judgment part which judges whether the mobile terminal is located in an indoor location or an outdoor location, based on the received power and the moving state.

Abstract: A layout design system is provided with a storage device, a design processor, and an output device. The storage device stores interconnection-routed layout data of an integrated circuit. The design processor detects an interconnection violating a timing constraint based on the interconnection-routed layout data and modifies the interconnection-routed layout data so as to provide a space around the detected interconnection and to change a width of the detected interconnection by using the provided space. The output device outputs the modified interconnection-routed layout data.

Abstract: An exemplary object of the present invention is to facilitate the management of identification information in a microcomputer having a flash memory. A system 1 in accordance with an example embodiment of the present invention includes flash programming section 2 that writes information including a user program to a flash memory 21, first user program transmitting section 3 that transmits the user program from the user side to the host side through the communication network 15, user program receiving section 4 that receives the user program, custom code assigning section 5 that assigns a custom code that enables the discrimination of the user program, first custom code transmitting section 6 that transmits the custom code to the flash programming section 2, and custom code storing section 7 that stores the custom code within the microcomputer 11.

Abstract: A MISFET includes a drain diffusion layer of a first conductivity type, a source diffusion layer of the first conductivity type, a gate electrode, and a substrate/well of a second conductivity type. In the MISFET, first diffusion layers of the first conductivity type are provided at two or more positions at predetermined intervals with an isolation therebetween respectively. The two or more positions are facing at least two sides of the element isolation insulation around the drain diffusion layer. A second diffusion layer of the second conductivity type is provided so as to be close to or to come in contact with the source diffusion layer.

Abstract: An electronic device of the present invention has a substrate; an electro-conductive pattern (electrodes) provided over the substrate; a semiconductor chip mounted over the substrate, and electrically connected with the electrodes; a resin cap provided over the substrate and composed of two or more resin layers to hollow-sealing the semiconductor chip; and an adhesive layer (metal-resin adhesion maintenance layer) bonding the resin cap with the electrode.

Abstract: At least a part of an outer edge of a surface where a circuit forming region, for example, of a semiconductor substrate that forms a semiconductor chip is arranged (a region surrounded by a scribe line around the circuit forming region) is cut or polished, so as to form a smooth slope is chamfered non-parallel and non-vertical to the circuit forming region. Then, a code indicating management information is assigned to the slope. Further, a plurality of semiconductor chips are stacked to manufacture a semiconductor device.

Abstract: Disclosed is a phase shifting circuit that includes a PLL loop in which a reference frequency received is branched into first and second signals. The first signal becomes one input to a phase comparator and the second signal becomes another input to the phase comparator after being shifted in phase via a phase shifter. The output of the phase comparator is supplied to one input terminal of a differential amplifier via a low-pass filter. The amount of phase shift of the phase shifter is controlled by the output signal of the differential amplifier. The amount of phase shift of the phase shifter is decided by a reference voltage applied to another input terminal of the differential amplifier.

Abstract: A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit to which electric power is supplied from first power supply wiring, and first ground wiring to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit to which electric power is supplied from second power supply wiring, and second ground wiring coupled to the second circuit unit. The first circuit unit includes a first interface circuit unit, and the second circuit unit includes a second interface circuit unit configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The second interface circuit unit is placed in the vicinity of the first interface circuit unit according to a determined arrangement.