Patents Assigned to NEC Electronics
  • Publication number: 20090244866
    Abstract: The circuit device includes a first transmitting inductor, a first insulating layer, a first receiving inductor, and a second receiving inductor. The first transmitting inductor is constituted of a helical conductive pattern and receives a transmitted signal. The first receiving inductor is located in a region overlapping the first transmitting inductor through the first insulating layer. The first receiving inductor is constituted of a helical conductive pattern, and generates a received signal corresponding to the transmitted signal input to the first transmitting inductor. The second receiving inductor is connected in series to the first receiving inductor, and constituted of a helical conductive pattern. The second receiving inductor generates a voltage in an opposite direction to that generated by the first receiving inductor, in response to a magnetic field of the same direction.
    Type: Application
    Filed: June 5, 2009
    Publication date: October 1, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Masaya Kawano, Yasutaka Nakashia
  • Publication number: 20090243400
    Abstract: A semiconductor device according to the present invention includes: a first internal terminal; a second internal terminal; a first switching circuit coupled to the second internal terminal to switch between a state in which the second internal terminal is electrically coupled to a first reference electric potential and a state in which the second internal terminal is not electrically coupled to the first reference electric potential; a second switching circuit coupled to the second internal terminal to switch between a state in which the second internal terminal is electrically coupled to a second reference electric potential and a state in which the second internal terminal is not electrically coupled to the second reference electric potential; and a comparator coupled to the first internal terminal and the second internal terminal to compare an electric potential of the first internal terminal with an electric potential of the second internal terminal, in which the first switching circuit and the second swi
    Type: Application
    Filed: August 14, 2008
    Publication date: October 1, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Hiroyoshi Fukuda
  • Publication number: 20090243110
    Abstract: A semiconductor device includes a semiconductor substrate having an element region on a surface thereof, an active element being formed in the element region. An insulating layer is formed on the semiconductor substrate and covers the active element. An inductor is formed on the insulating layer and overlaps with the active element.
    Type: Application
    Filed: May 13, 2009
    Publication date: October 1, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Yoshinori Muramatsu, Yasutaka Nakashiba
  • Publication number: 20090245454
    Abstract: A signal processing device includes a detecting part that detects intensity of an input signal, a timer part that includes a time constant circuit and measures time based on a time constant of the time constant circuit, and a determination circuit that counts the number of times of switching of the input signal detected by the detecting part within the time measured by the time constant circuit.
    Type: Application
    Filed: March 30, 2009
    Publication date: October 1, 2009
    Applicants: NEC Electronics Corporation, NEC Corporation
    Inventors: Noriaki Matsuno, Yoshinori Horiguchi, Yuu Yamaguchi, Orie Tsuzuki, Tomonobu Kurihara, Isao Sakakida, Tadashi Maeda, Tomoyuki Yamase
  • Publication number: 20090242980
    Abstract: In a semiconductor device, a memory region and a logic region are provided on one silicon substrate. A trench is provided in the silicon substrate in the memory region, a memory cell transistor is provided in the memory region and a logic transistor is provided in the logic region. The memory cell transistor includes a first gate electrode constituted by a metal material. The first gate electrode is provided to be buried in the trench and to protrude outside of the trench. The logic transistor includes a second gate electrode constituted by same material as the metal material constituting the first gate electrode.
    Type: Application
    Filed: February 27, 2009
    Publication date: October 1, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Ken Inoue
  • Publication number: 20090242268
    Abstract: A semiconductor device according to the present invention includes first through fourth internal terminals placed along the perimeter of a substrate, a circuit coupled to the first internal terminal, a first external terminal coupled to the second internal terminal, a second external terminal coupled to the third internal terminal, and a third external terminal coupled to the fourth internal terminal. The circuit outputs a signal indicative of a connection state the first internal terminal and the first external terminal. A distance between centers of the first and second internal terminals is L1 in a direction parallel to one side of the substrate beside which the first external terminal is placed. A distance between centers of the third and fourth internal terminals is L2 in a direction parallel to one side of the substrate beside which the second and third external terminals are placed. The distance L1 is set smaller than the distance L2.
    Type: Application
    Filed: August 13, 2008
    Publication date: October 1, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Hiroyoshi Fukuda
  • Patent number: 7595776
    Abstract: A drive circuit for a display apparatus includes a gradation voltage generation circuit and a D/A conversion circuit. The gradation voltage generation circuit generates a plurality of different first gradation voltages and a plurality of different second gradation voltages. The D/A conversion circuit drives a light emitting element of a pixel through a data line with a gradation voltage based on one of the first gradation voltages as a first specific gradation voltage in a precharge period and drives the light emitting element of the pixel through the data line with a gradation current based on one of the second gradation voltages as a second specific gradation voltage. The D/A conversion circuit includes a voltage driver to drive the light emitting element, and a current driver to drive the light emitting element.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: September 29, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Yoshiharu Hashimoto, Teru Yoneyama
  • Patent number: 7595538
    Abstract: A P-type MOSFET 120 includes a semiconductor substrate (N-well 102b); a gate insulating film formed on the semiconductor substrate, composed of a high-dielectric-constant film 108 which contains a silicate compound containing a first element selected from the group consisting of Hf, Zr and any of lanthanoids, together with N; a gate electrode formed on the gate insulating film, and is configured by a polysilicon film 114 containing a P-type impurity; and a blocking oxide film 110 formed between the gate insulating film and the gate electrode, blocking a reaction between the first element and the polysilicon film 114, and having a relative dielectric constant of 8 or above.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: September 29, 2009
    Assignee: Nec Electronics Corporation
    Inventor: Ichiro Yamamoto
  • Patent number: 7595560
    Abstract: An improved reliability of a junction region between a bonding wire and an electrode pad in an operation at higher temperature is presented. A semiconductor device 100 includes a semiconductor chip 102 provided on a lead frame 121, which are encapsulated with an encapsulating resin 115. Lead frames 119 are provided in both sides of the lead frame 121. A portion of the lead frame 119 is encapsulated with the encapsulating resin 115 to function as an inner lead 117. The encapsulating resin 115 is composed of a resin composition that contains substantially no halogen. Further, an exposed portion of the Al pad 107 provided in the semiconductor chip 102 is electrically connected to the inner lead 117 via the AuPd wire 111.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: September 29, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Mitsuru Ohta, Tomoki Kato
  • Patent number: 7595561
    Abstract: In a semiconductor device including an internal circuit, multiple rows of peripheral circuit units are electrically connected to the internal circuit and arranged on at least one peripheral edge of the internal circuit. Also, a plurality of pads are arranged on the peripheral edge of the internal circuit. Each of the pads is electrically connected to one of the peripheral circuit units.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: September 29, 2009
    Assignee: Nec Electronics Corporation
    Inventors: Shingo Ichikawa, Miho Hirai
  • Patent number: 7596036
    Abstract: A memory control circuit according to an embodiment of the present invention includes: a writable/readable memory; a comparison unit comparing write data to write in the memory with read data that is read from a memory address where the write data is written; a comparison result storage unit storing a comparison result compared by the comparison unit in association with the memory address; and a control unit controlling retry processing of rewriting the write data to the memory address determined to be unverified based on the stored comparison result.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: September 29, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Takao Kondo, Youji Terauchi, Yuuji Kuge
  • Patent number: 7595537
    Abstract: In a semiconductor device, a well region is formed in a semiconductor substrate, a transistor-formation region is defined in the well region. An electrostatic discharge protection device is produced in the transistor-formation region, and features a multi-finger structure including a plurality of fingers. A guard-ring is formed in the well region so as to surround the transistor-formation region, and a well blocking region is formed in the well region between the transistor-formation area and the guard-ring. A substrate resistance determination system is associated with the electrostatic discharge protection device to determine a substrate resistance distribution at the transistor-formation area such that snapbacks occur in all the fingers in a chain-reaction manner, and such that occurrence of a latch-up state is suppressed.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: September 29, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Noriyuki Kodama, Hitoshi Irino
  • Patent number: 7595671
    Abstract: A PLL circuit according to an embodiment of the present invention includes: a phase comparing circuit comparing phases of a reference clock signal and a feedback clock signal to output a voltage-up signal and a voltage-down signal based on the phase difference; a first charge pump circuit generating a first current based on the voltage-up signal and the voltage-down signal; a dummy signal generating circuit outputting a dummy signal having substantially the same pulse width as a pulse width of the voltage-up signal or the voltage-down signal in sync with the voltage-up signal or the voltage-down signal; a second charge pump circuit generating a second current based on the dummy signal; and a voltage-controlled oscillator controlling an output clock frequency based on a differential voltage between a first voltage generated in accordance with the first current and a second voltage generated in accordance with the second current.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: September 29, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Masafumi Watanabe
  • Patent number: 7596717
    Abstract: A microcomputer includes a first memory area that stores a first program, a second memory area that stores a second program, a CPU that operates in accordance with the first program and the second program, and a debug circuit that controls to block the CPU from accessing the first memory area and prompt the CPU to access the second memory area during debugging of the first program.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: September 29, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Akiko Terao
  • Publication number: 20090239377
    Abstract: A semiconductor device includes a semiconductor substrate, a copper-containing metal interconnect over the semiconductor substrate, and a copper-containing connection plug, and the metal interconnect includes metal elements other than copper, and a concentration of different metal elements in a connection portion between the metal interconnect and the connection plug is higher than a concentration of the different metal elements in a center portion of the metal interconnect, and higher than a concentration of different elements in upper face portion of the metal interconnect other than the connection portion.
    Type: Application
    Filed: June 5, 2009
    Publication date: September 24, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Koichi Motoyama
  • Publication number: 20090237108
    Abstract: Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-supply-noise cancelling circuit connected between the input terminal and the output terminal to generate a current that cancels a current flowing from the power supply (VDD0) to the output terminal or a current flowing from the output terminal to the ground (GND0), based on a potential difference between the input terminal and the output terminal.
    Type: Application
    Filed: March 23, 2009
    Publication date: September 24, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Masashi Kurokawa, Kenichi Kawakami
  • Publication number: 20090237851
    Abstract: A semiconductor integrated circuit device includes an output transistor, an overcurrent detection circuit and overcurrent limitation circuit. The overcurrent detection circuit includes a first transistor detecting an overcurrent of the output transistor. The overcurrent limitation circuit is connected between a gate and a source of the output transistor. The overcurrent limitation circuit includes a plurality of resistance elements and a diode connected in series between the gate and the source of the output transistor in series, and a second transistor whose gate is connected to a connection point between the resistance elements and that is cascade connected to the first transistor.
    Type: Application
    Filed: March 17, 2009
    Publication date: September 24, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Mitsuru Yoshida
  • Publication number: 20090236641
    Abstract: A manufacture method is provided for forming a semiconductor device. The method includes: forming a plurality of gate electrodes through etching a conductive film deposited on a semiconductor substrate; forming a first nitride film to cover the gate electrodes; partially exposing the semiconductor substrate in a region between adjacent two of the gate electrodes through performing an etch-back process on the first nitride film; thermally oxidizing a residual of the gate electrode film remaining in the region between the adjacent two of the gate electrodes to change the residual into an thermal oxide film; and forming a contact in the region between the adjacent two of the gate electrodes.
    Type: Application
    Filed: March 23, 2009
    Publication date: September 24, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Kazuhiro Tasaka
  • Publication number: 20090236523
    Abstract: An analysis apparatus for a semiconductor device, capable of attaining highly efficient analysis of failure in the semiconductor device by a secondary-electron image, including: a region determination unit which determines a region constituting a secondary-electron image of a semiconductor device to be analyzed obtained by irradiating charged particle beam, based on the secondary-electron image and design data of the semiconductor device as a source of comparison; a material identification unit which identifies a material of each configuration of an image obtained by the region determination unit, based on the design data of the semiconductor device; a unit which calculates a potential in the each region identified by the material identification unit, based on the design data of the semiconductor device; a unit which colors each region of an image obtained by the material identification unit in accordance with the potential and generates a dummy good-product secondary-electron image; and a unit which displays
    Type: Application
    Filed: March 20, 2009
    Publication date: September 24, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Toyokazu Nakamura
  • Publication number: 20090237145
    Abstract: A semiconductor device includes an interface circuit that varies drive ability according to a control signal, and a control circuit that generates the control signal according to a range of an output voltage of the interface circuit. The interface circuit and the control circuit are provided on one chip.
    Type: Application
    Filed: February 26, 2009
    Publication date: September 24, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Masaki Naganawa