Abstract: A USB controller according to one aspect of the present invention is a USB controller incorporated in a USB device, the USB controller including a RAM that stores data transferred through a USB port or a CPU bus, and a register that holds a setting for determining to which one of a region for host used for a host function and a region for peripheral used for a peripheral function a part of the RAM is allocated.

Abstract: An input circuit, includes a first buffer circuit having an output signal terminal connected to an output; a capacitor having one end connected to an input signal terminal, and the other end connected to an input of the first buffer circuit; a first differential amplification circuit receiving a voltage of a first external power source terminal and an output of a second buffer circuit; a second differential amplification circuit receiving a voltage of a second external power source terminal and an output of a third buffer circuit; a first resistance having one end connected to an output of the first differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit; and a second resistance having one end connected to an output of the second differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit.

Abstract: A display driving circuit includes an amplifier circuit including an output stage including first and second MOS transistors which are complementary to each other to perform a push-pull operation, an output terminal, a switch element provided between an output end of the output stage and the output terminal, and a controller which enables the first and second MOS transistors to exclusively turn on and off.

Abstract: An integrated circuit includes multiple memory circuits including memory cell arrays different in size, a BIST circuit which has a cell sequential transition test processor and which outputs a test cell address, a transition direction specification signal and an active signal. The integrated circuit has adjustment circuits which are provided respectively for the memory circuits and which replace the test cell address with the test cell address in a memory cell array area, or which convert the active signal into a signal indicating non-execution when the test cell address outputted from the BIST circuit corresponds to a cell in a virtual cell array being in an area outside the memory cell array.

Abstract: A semiconductor apparatus includes an internal layer where a first power supply line to provide a first power supply to transistors in a layout cell and an internal cell line to connect transistors in the layout cell are placed, an input/output line connected with an input/output terminal of the layout cell is placed, and a shield line which is placed between the internal layer and the input/output line so as to cover the internal layer and the first power supply line.

Abstract: Disclosed is a semiconductor memory device including a plurality of diffusion regions, select gates, word lines, and common diffusion regions. The plurality of diffusion regions are extended in the surface of a substrate in a memory cell area, being spaced apart to one another in one direction, and constitute bit lines. The select gates are configured to be extended in one direction over the substrate. The word lines are extended in a direction orthogonal to the one direction and cross the select gates. The bit line diffusion regions are formed by self alignment using floating gates over the sidewalls of select gates as masks, and each of the bit line diffusion regions is separated into at least two regions in the one direction. The common diffusion regions are provided in an area of the isolation in a direction orthogonal to the one direction.

Abstract: A semiconductor device according to an embodiment of the present invention includes a semiconductor chip. The semiconductor chip includes a semiconductor substrate, an interconnect layer, a back electrode (first working electrode), and a back dummy electrode (first dummy electrode). On the semiconductor substrate, the interconnect layer including an interconnect is provided. On a back surface of the semiconductor substrate, the back electrode is provided in electrical connection to the interconnect. On the back surface, also the back dummy electrode is provided, which is electrically insulated from the interconnect.

Abstract: The removing solution containing a cerium (IV) nitrate salt, periodic acid or a hypochlorite can be applied to metals containing copper, silver or palladium and also to metals containing other metals having a relatively large oxidation-reduction potential.

Abstract: Reduction in power consumption of a counter circuit for continuous operation is demanded. Therefore, provided is a counter circuit including: a first counter of m bits for counting and storing a value of a predetermined bit width according to an input clock; a clock transmission control circuit for controlling whether to transmit the input clock based on a value output according to a counting result of the first counter; and a second counter of n bits for counting and storing another value of the predetermined bit width according to the input clock transmitted from the clock transmission control circuit.

Abstract: A flux for soldering of the present invention, in connecting a mounting pad exposed on a board to a solder ball, is applied onto at least one of a surface of the mounting pad and the solder ball. The flux for soldering contains a solvent, and the solvent contains a compound, which is represented by a general formula (1) and having a boiling point of 218° C. or higher and 240° C. or lower: R1-R2n-OH . . . (1).

Abstract: When inputted with a loading plan table file including item names to be loaded into a process line and the number of item names to be loaded, an equipment loop is executed for each equipment. The equipment loop includes an item name loop and a machine-type loop. In the item name loop, a condition group representing a combination of machine types is acquired for each process. In the machine-type loop, distribution factor data for each machine type is acquired for each condition group, and data of a required number of pieces to be processed by process and machine type, the data to be assigned to each machine type on the basis of the distribution factor data. Based on this data of the number of pieces to be processed by process and machine type, machine-type load factor data for each machine type is determined for each equipment.

Abstract: The pattern matching processing system includes: a recognition pattern-storage unit which stores a first image data obtained by picking up an image of at least a portion of a lead frame or a substrate of a first object and the second image data obtained by picking up an image of at least a portion of a lead frame of a second object that is different from the first object, respectively, and also stores one of the first image data and the second image data as an ordinary recognition pattern, and the other as an auxiliary recognition pattern; and a recognition unit, which recognizes input image data by a first pattern matching with the ordinary recognition pattern stored in the recognition pattern-storage unit, and also carries out the second pattern matching with the auxiliary recognition pattern when an error is caused in the first pattern matching.

Abstract: Disclosed is an apparatus including an odd data receiving unit that receives an input signal, an even data receiving unit that also receives the input signal, and a pattern filter. The odd data receiving unit samples a half-rate DFE equalized signal with an odd data timing clock to output data decision data. The odd data receiving unit also samples both the half-rate DFE equalized signal and a non-half-rate DFE equalized signal with an odd edge timing clock having the phase shifted by 90 degrees from the odd data timing clock to output resulting edge decision data. The even data receiving unit samples the half-rate DFE equalized signal with an even data timing clock having the phase shifted by 180 degrees from the odd data timing clock to output data decision data.

Abstract: Provided is a drive signal generating apparatus including: an arithmetic section that calculates an approximate expression to approximate variations of multiple detected values each representing one of a position of an optical pickup section and an amount of positional deviation of the optical pickup section with respect to a current target position, the position of the optical pickup section being sequentially detected when the optical pickup section moves stepwise toward multiple target positions set in advance on a drawing surface of a drawing target; and a drive signal generation section that generates a second drive signal synchronized with a first drive signal for causing the optical pickup section to move stepwise, the second drive signal having a signal value corresponding to an approximate value calculated by substituting a value associated with each of the multiple target positions into the approximate expression so as to move an optical component provided in the optical pickup section.

Abstract: In a method of designing a photo-mask, a graphic pattern as a target of development simulation is divided into a plurality of sub graphic patterns which are respectively assigned with a plurality of orthogonal coordinate systems which are not orthogonal to each other. A model-based OPC (optical proximity correction) is performed on each of the plurality of sub graphic patterns by moving sides of the sub graphic pattern in directions parallel to coordinate axes of the orthogonal coordinate system assigned to the sub graphic pattern.

Abstract: An electrical fuse including a polysilicon layer; a silicide layer formed over the polysilicon layer; and a first metal contact and a second metal contact arranged over the silicide layer, while being spaced from each other, the electrical fuse being configured so that the silicide layer, after disconnection, is excluded from a region right under the second metal contact, and from a region between the second metal contact and the first metal contact is provided.

Abstract: A differential amplifier includes a first differential pair formed by transistors of a first conductivity type, to receive input signals and output first differential-mode currents, a first current amplifier section to output a first output source current and a first output sink current to a first output terminal and a second output terminal, respectively, based on the first differential-mode currents, a second differential pair formed by transistors of a second conductivity type, to receive the input signals and output second differential-mode currents, and a second current amplifier section to output a second output source current and a second output sink current to the first output terminal and the second output terminal, respectively, based on the second differential-mode currents.

Abstract: Disclosed is a differential amplifier of the present invention includes a differential pair differentially receiving a signal, a current source connected between a first voltage supply and the differential pair, for driving the differential pair, a current-to-voltage converter circuit receiving output currents of the differential pair and producing first and second voltage signals, first and second transistors of mutually different conductivity types connected in series between the first voltage supply and a second voltage supply and respectively receiving the first and second voltage signals at control terminals thereof, a third transistor connected between the second voltage supply and an output terminal and receiving the first voltage signal at a control terminal thereof, and a fourth transistor of the same conductivity type as that of the third transistor, the fourth transistor being connected between the output terminal and the first voltage supply and having a control terminal thereof connected to a con

Abstract: An access control method is achieved by providing a flash memory which includes a set of a plurality of blocks, each of which has at least one data area and a flag area. The method is achieved by further referring to flag data written in the flag area of each of the plurality of blocks, to determine whether one of the plurality of blocks is valid, and further reading out data from the block when it is determined based on the flag data that the block is valid.

Abstract: Disclosed is a canceller device comprising a subcanceller for compensating the sampling phase shift of a plurality of analog-to-digital convert circuits for receiving a common input analog signal, converting the analog signal into digital signals responsive to respective sampling clock signals with different phases to each other, and for outputting the digital signals, a main canceller for canceling echo/cross-talk from the signal output from analog-to-digital convert circuits whose the sampling phase shifts have been compensated, and a compensation range selection circuit for determining the range of the sampling phase shift for being compensated by the subcanceller based on the tap coefficients of the main canceller.