Patents Assigned to NEC Electronics
  • Semiconductor device
    Publication number: 20090096074
    Abstract: Disclosed herewith is a semiconductor device, which includes a semiconductor chip; a lead device that includes an island for mounting the semiconductor chip and having an area smaller than that of the semiconductor chip at its contact surface, as well as plural hanging leads for supporting the island and coming in contact partially with the semiconductor chip; a mounting material provided on a contact surface between each of the island and hanging leads and the semiconductor chip so as to adhere the semiconductor chip to the island and the hanging leads; and sealing resin for sealing the semiconductor chip. The modulus of elasticity of the mounting material is lower than that of the sealing resin. The mounting material is further coated on the back surfaces of the contact surfaces of the island and the hanging leads.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 16, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Naoto Kimura
  • Semiconductor device having high frequency wiring and dummy metal layer at multilayer wiring structure
    Publication number: 20090096061
    Abstract: A semiconductor device includes, a metal wiring, which functions as an inductor or transformer, formed on a first portion of a semiconductor substrate, a plurality of first dummy layers formed in a first density on the first portion of the semiconductor substrate, a plurality of second dummy layers formed in a second density on a second portion of the semiconductor substrate, the second portion surrounding the first portion, and a plurality of third dummy layers formed in a third density higher than the first and second densities on a third portion of the semiconductor substrate, the third portion surrounding the second portion.
    Type: Application
    Filed: October 2, 2008
    Publication date: April 16, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Shinichi Uchida
  • Semiconductor integrated circuit device having control circuit to selectively activate decoupling cells
    Publication number: 20090096516
    Abstract: The semiconductor integrated circuit device includes a plurality of decoupling cells that suppress power noise respectively, a plurality of power switches that connect the decoupling cells to a power line respectively, and a control circuit that controls the number of power switches selected from among the plurality of power switches and to be turned on according to power noise to be changed according to the operation state of each of internal circuits driven by a power supplied from the power line.
    Type: Application
    Filed: September 29, 2008
    Publication date: April 16, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Hidenari Nakashima
  • Semiconductor integrated circuit device and inspection method of the same
    Patent number: 7518936
    Abstract: A semiconductor integrated circuit device includes: a plurality of memories and a judgement circuit. Each of plurality of memories is configured to include a Built-in Self Test (BIST) circuit that examines a possibility of repairing a defect and outputs a repair possibility signal indicating the possibility. The judgement circuit is configured to judge whether or not all of the plurality of memories can be repaired based on a plurality of the repair possibility signals. Each of the plurality of the repair possibility signals is outputted from one of the plurality of memories.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: April 14, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Hiroyuki Kobatake
  • Decoding apparatus and decoding method
    Patent number: 7519897
    Abstract: To provide a decoder and decoding method capable of reducing the number of times received data is decoded. A decoder according to the present invention includes: a Viterbi decoder decoding received data; a decode data length storage area storing a decode data length; a decoded data temporary storage area storing temporary storage data as decoded data up to a decode data length; a maximum data storage memory storing maximum decoded data as decoded data up to a maximum data length; a maximum-likelihood detection circuit selecting a decode data length based on likelihood information; and a decoded data reconstruction circuit replacing a part of maximum decoded data with temporary decoded data.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: April 14, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Takeshi Hashimoto
  • Semiconductor device with multilayer interconnection structure
    Patent number: 7518243
    Abstract: A semiconductor device with a multilayer interconnection structure comprises a semiconductor substrate, a plurality of metal wiring layers provided on the semiconductor device and electrically insulated from the upper and lower layers by an interlayer insulation film, and via holes penetrating through the interlayer insulation film and connecting the wirings of the first metal wiring layer and the second metal wiring layer positioned above the first metal wiring layer. And, potential of predetermined wiring of the first metal wiring layer is electrically floating from the semiconductor substrate, and a capacitance value between the wiring of the first metal wiring layer and the semiconductor substrate per one via provided on the predetermined wiring of the first metal wiring layer is a predetermined value or less.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: April 14, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Yoshitake Tokumine
  • Semiconductor testing device
    Patent number: 7518242
    Abstract: A semiconductor device has a bonding pad configured to be bonded to a bonding member, a test pad configured to contact with a test probe at a test, and an internal circuit electrically connected to the bonding pad and the test pad. The bonding pad overlaps with the internal circuit in a direction vertical to a surface of a semiconductor chip. The test pad does not overlap with the internal circuit in the direction.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: April 14, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Miho Hirai
  • Frequency multiply circuit using SMD, with arbitrary multiplication factor
    Patent number: 7519087
    Abstract: Disclosed is a frequency multiply circuit for outputting an output signal obtained by variably multiplying the frequency of an input signal includes a synchronous delay circuit, a multiplexing circuit, and a control circuit. The synchronous delay circuit includes a period measuring delay circuit for measuring the period of the input signal and delay reproducing delay circuits each with a delay time thereof variably set based on the period measured by the period measuring delay circuit, for respectively reproducing the delay time. The multiplexing circuit receives a plurality of signals of different phases output from the synchronous delay circuits, for multiplexing. The control circuit variably sets the number of the delay stages of the period measuring delay circuit and the numbers of the stages of the delay reproducing delay circuits, according to the set frequency-multiplication factor.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: April 14, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Mitsuaki Tagishi
  • Optical disk device
    Publication number: 20090092030
    Abstract: Provided is an optical disk device to output a reproduction signal to reproduce an optical disk, including: a light output circuit to output light having a high frequency superimposed thereon; a first light receiving circuit to receive the light to output a first voltage corresponding to an amount of the light; a second light receiving circuit to output a second voltage corresponding to an amount of reflected light from the optical disk; an arithmetic circuit to output a calculation result based on a difference between the first voltage and the second voltage; and a reproduction signal generating circuit to control one of the first voltage and the second voltage based on the calculation result to generate the reproduction signal to reproduce the optical disk.
    Type: Application
    Filed: September 10, 2008
    Publication date: April 9, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Tadashi Jahana, Seiji Kawata
  • SEMICONDUCTOR DEVICE
    Publication number: 20090091004
    Abstract: A semiconductor device according to one aspect of the present invention includes a semiconductor substrate, an interlayer insulating film formed over the semiconductor substrate, a metal wiring formed over the interlayer insulating film, a protective insulating film formed on the metal wiring, and a resin film formed within a region having one side shorter than a predetermined length on the protective insulating film. The resin film covers all regions in which an interval of the metal wirings is equal to or less than a predetermined interval.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 9, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Hirosada KOGANEI
  • Multi-valued mask ROM
    Publication number: 20090090957
    Abstract: A mask ROM is provided with a plurality of memory cells each including first and second nodes, and a transistor having a source and drain connected to the first and second nodes, respectively. A first memory cell out of the plurality of memory cells further includes a first resistive interconnection which provides an electrical connection between the first and second nodes. The resistance of the first resistive interconnection is adjusted depending on data stored onto the first memory cell.
    Type: Application
    Filed: October 2, 2008
    Publication date: April 9, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Takayuki Onda
  • SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SAME
    Publication number: 20090094494
    Abstract: A semiconductor integrated circuit includes a semiconductor memory circuit, an address input unit to generate an input address and to input the input address into the semiconductor memory circuit, the address input unit repeating generating and inputting from a start address to a end address, and an output data processor to select a select data and to count a value of the select data. The input address specifies data stored in the semiconductor memory circuit. The select data is a count object of output data read out from the semiconductor memory corresponding to the input address.
    Type: Application
    Filed: October 3, 2008
    Publication date: April 9, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Toshio Takeshima
  • FILTER OPERATION UNIT AND MOTION-COMPENSATING DEVICE
    Publication number: 20090094303
    Abstract: A filter operation unit that performs a multiply-accumulate operation on input data and a filter coefficient group including a plurality of coefficients using Booth's algorithm. The filter operation unit includes: at least two filter multiplier units that multiply the input data and a difference between adjacent filter coefficients in a filter coefficient group to obtain multiplication results; and an adder that adds the multiplication results of the multiplier units adjacent to each other. The filter multiplier units each include: a partial product generation unit that repeatedly generates a partial product according to Booth's algorithm; and an adder that cumulatively adds the partial products generated by the partial product generation unit.
    Type: Application
    Filed: September 24, 2008
    Publication date: April 9, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Yoichi KATAYAMA
  • Semiconductor device capable of suppressing variation of current or voltage to be supplied to external circuit
    Patent number: 7515150
    Abstract: A semiconductor device is capable of suppressing variations of a current or a voltage to be supplied to an external circuit. The semiconductor device has a plurality of unit areas arrayed in one direction, and components in the unit areas are arranged in the same shape and the same layout in the unit areas. A holding capacitor for holding a voltage is surrounded by an interconnect kept at ground potential. Interconnects at ground potential are inserted in areas where reference current interconnects for supplying reference currents to functional blocks (1-bit DCC circuit regions) and gradation digital data interconnects and storage timing signal interconnects cross each other vertically, the interconnects being disposed between these reference current interconnects, gradation digital data interconnects and storage timing signal interconnects.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: April 7, 2009
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventors: Katsumi Abe, Masamichi Shimoda
  • Method of manufacturing a semiconductor apparatus
    Patent number: 7514307
    Abstract: A method of manufacturing a semiconductor apparatus of the present invention comprises forming body diffusion layer, a gate electrode, and an interlayer dielectric over an surface of a semiconductor substrate, forming a photoresist having an opening in a region overlapping with a part of the body diffusion layer, removing the interlayer dielectric to form an opening using the photoresist as a mask, forming a body contact diffusion layer by implanting ion in the opening of the interlayer dielectric using the photoresist as a mask, forming a source contact by removing neighboring portion of the opening of the interlayer dielectric using the photoresist as a mask after the body contact diffusion layer 13 is formed, and removing the photoresist.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: April 7, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Kinya Ootani
  • Semiconductor device
    Patent number: 7514766
    Abstract: A semiconductor device in which the threshold voltage of transistors is controlled through the applied substrate bias and having relatively small size. The semiconductor device includes: a clock signal line; a shield wiring for shielding the clock signal line from another interconnection; and a substrate bias generating circuit. The substrate bias is applied through the shield wiring to a region on which a transistor is formed. The threshold voltage of the transistor depends to the substrate bias applied to the transistor.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: April 7, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Masatoshi Yoshida
  • Semiconductor integrated circuit having oscillator frequency compensation function
    Patent number: 7515008
    Abstract: It is desired that the temperature dependency of the frequency of a oscillator in a semiconductor IC is compensated in high precision. First signal voltage having temperature dependency and second signal voltage set to be constant independently from the temperature are outputted and A/D converted into first and second converted signals. And the compensation code is generated in response to the ratio between the first and second converted signals. The temperature dependency of the frequency of the oscillator can be compensated by using the compensation code.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: April 7, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Shuichi Ide
  • Semiconductor device and wire bonding method therefor
    Patent number: 7514800
    Abstract: A semiconductor device (10) that may have a wire bonding structure having reduced interference between bond wires and a path of a capillary has been disclosed. Semiconductor device (10) may include bond pads (12) arranged in a line along an edge of a semiconductor chip (14) and conductive fingers (16) arranged on a substrate (18). Bond pads (12) may be electrically connected to conductive fingers (16) with bond wires (20). Bond wires (20) may be divided into a first group having a relatively short length and a second group having a relatively long length. The bond wires (20) in the first group may have bonding points on a bonding pad (12) that is closer to an edge of semiconductor chip (14) than bonding points of bond wires (20) in the second group. In this way, spacing between bond wires (20) already formed and a capillary forming an adjacent bond wire may be increased.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: April 7, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Tsuyoshi Kida
  • Layout design program, layout design device and layout design method for semiconductor integrated circuit
    Patent number: 7516434
    Abstract: A computer program product for floorplanning design of a semiconductor integrated circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to perform the following steps (a) to (d). The step (a) is the step of placing circuit blocks based on a netlist. The step (b) is the step of estimating an interconnection length between two of the placed circuit blocks based on the netlist and positions of the placed circuit blocks. The step (c) is the step of judging whether the estimated interconnection length satisfies timing constraints for connections among the circuit blocks, based on relation data indicating relations among interconnection lengths and timings. The step (d) is the step of outputting the judgment result.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: April 7, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Hideyuki Okabe
  • Level shifter circuit
    Patent number: 7514960
    Abstract: A level shifter circuit has first to fourth transistors and a resistive element. The first transistor is activated in response to a logic signal whose high level voltage is a first voltage. The second transistor is activated in response to the inverse logic signal. Each of the first and second transistors is connected between a power supply line for supplying a second voltage and a ground line. The third transistor is connected to a drain of the first transistor through a first node. The fourth transistor is connected to a drain of the second transistor through a second node. A gate of the third transistor is connected to the drain of the second transistor through the second node. A gate of the fourth transistor is connected to the drain of the first transistor through the first node. The resistive element is connected between the first node and the second node.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: April 7, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Hiroshi Shimaya