Patents Assigned to NEC Electronics
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Publication number: 20090135953Abstract: A receiving circuit includes a frame memory to store received data of one frame, a de-rate matching circuit to generate data before encoding by reading the received data from the frame memory and performing de-rate matching in a reverse manner to rate matching performed on the received data at a transmitting end, and a TTI memory to store the data before encoding.Type: ApplicationFiled: November 3, 2008Publication date: May 28, 2009Applicants: NEC Electronics Corporation, NEC CorporationInventors: Takeshi Hashimoto, Kazuhiro Ishida
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Publication number: 20090138963Abstract: A CPU contained in an information processing apparatus in accordance an exemplary embodiment of the present invention outputs an access request including first access destination address information by a first program, and outputs a check request including second access destination address information when the execution program is switched from the first program to a second program as a result of a program call from the first program to the second program. A protection setting check portion contained in the information processing apparatus checks whether or not the check request including the second access destination address information conforms to protection setting for the first program based on memory protection information that is established in a memory protection information storage portion to detect a violation by a memory access request by the first program.Type: ApplicationFiled: November 13, 2008Publication date: May 28, 2009Applicant: NEC Electronics CorporationInventors: Junichi Sato, Hitoshi Suzuki
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Publication number: 20090134928Abstract: In the existing technique in which the attenuation characteristic of an attenuator is adjusted by a voltage value, there are problems that a scale of a circuit of the attenuator increases because a new circuit for supplying voltage such as a step-down circuit becomes necessary, and that a thermal noise and a shot noise are mixed in an output signal of the attenuator. To solve the above-mentioned problems, provided is an attenuator comprising a T-type two terminal pair network including first and second circuits connected in series, and a third circuit connected in shunt between these first and second circuits. A shunt capacitor is connected between the first and second circuits independent from the third circuit.Type: ApplicationFiled: November 5, 2008Publication date: May 28, 2009Applicant: NEC Electronics CorporationInventor: Junjirou Yamakawa
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Publication number: 20090137096Abstract: A clamp ring includes an abutting part abutting on the entire outer periphery of the main surface of a wafer when the wafer is fixed, and a brim part extending from the upper part of the abutting part to the inside of the wafer and provided so as not to abut on the main surface even when the wafer is fixed. The abutting part includes a first abutting section and a second abutting section, and a width of the first abutting section in a radial direction is greater than the width of the second abutting section in a radial direction.Type: ApplicationFiled: November 3, 2008Publication date: May 28, 2009Applicant: NEC Electronics CorporationInventor: Ryuji Tomita
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Publication number: 20090134523Abstract: A semiconductor chip includes a semiconductor chip region provided with a plurality of internal circuits, and a plurality of electrode pads provided proximate to an outer edge of the semiconductor chip region and each electrically connected to any one of the plurality of internal circuits. The plurality of electrode pads include: a long pad including a probe region with which a probe is brought into contact, and a bonding region provided in a position different from a position of the probe region, for bonding a wire; and a short pad for high frequency, which is formed to have a smaller pad area compared with the long pad and inputs/outputs a high frequency signal by employing a structure including the bonding region but the probe region.Type: ApplicationFiled: November 18, 2008Publication date: May 28, 2009Applicant: NEC Electronics CorporationInventor: Toru Yamazaki
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Publication number: 20090134495Abstract: A design method of a semiconductor device comprising forming a base wafer by using a plurality of semiconductor chips including a plurality of functional macros, generating macro test information by testing the plurality of function macros of the plurality of semiconductor devices; and picking a macro that is prohibited from being used out of the plurality of function macros based on the macro test information and a net list of user circuit. Since tests are carried out at the phase of a base wafer, it is possible to improve yield rates in the manufacture of semiconductor integrated circuits.Type: ApplicationFiled: November 13, 2008Publication date: May 28, 2009Applicant: NEC Electronics CorporationInventor: Keiichirou Kondou
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Publication number: 20090135801Abstract: The attenuation characteristics of an attenuator largely changes depending on the frequency of an input signal. Accordingly, a difference between the amounts of attenuation of gains of each two attenuators included in a communication device is not constant. In communications using the wireless USB, the difference needs to be in a range of 2 dB±1 dB. Thus, the communication device does not meet the standards of the wireless USB unless the difference between the amounts of attenuation of the attenuators is adjusted. In this regard, provided is a communication device including first and second attenuators that attenuate a signal. The second attenuator is provided with a regulator circuit that adjusts a relation between an amount of attenuation of the signal through the first attenuator and an amount of attenuation of the signal through the second attenuator.Type: ApplicationFiled: November 4, 2008Publication date: May 28, 2009Applicant: NEC Electronics CorporationInventor: Junjirou Yamakawa
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Publication number: 20090137084Abstract: Disclosed herewith is a semiconductor module manufacturing apparatus capable of reducing occurrence of warping of the wiring substrate, etc., as well as occurrence of failures of bonding between the wiring substrate and semiconductor chips, etc. without lowering the productivity. The semiconductor module manufacturing apparatus employs a batch reflowing process that heats one, two, or more wiring substrates and at least two or more semiconductor chips or semiconductor devices simultaneously. After the heating process, the semiconductor chips or semiconductor devices are heated and bonded on the wiring substrate. The apparatus includes at least a stage for chucking the wiring substrate fixedly; a heat source for heating the semiconductor chips or semiconductor devices out of contact therewith; and a controller for controlling the heating value of the heat source.Type: ApplicationFiled: November 18, 2008Publication date: May 28, 2009Applicant: NEC Electronics CorporationInventor: Tsuyoshi Kida
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Patent number: 7538428Abstract: A semiconductor device having macro circuit including concentrated fine interconnections and extension wiring for connecting the macro circuit and the outer circuit. The widths of the fine interconnections are less than 0.1 ?m. An end of the extension wiring is connected to at least two of fine interconnections of the macro circuit arranged in parallel. By this configuration, the possibility of disconnection at the portion where the end of the extension wiring and the fine interconnections are connected is suppressed.Type: GrantFiled: November 1, 2006Date of Patent: May 26, 2009Assignee: NEC Electronics CorporationInventor: Yoshihisa Matsubara
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Patent number: 7538643Abstract: A switch circuit 1 includes a unit circuit including capacitors 12, 14, an inductor 20, and a FET 30 (switching element). The capacitors 12, 14 are provided in a path P1 (first path) connecting I/O terminals 92, 94. The capacitors 12, 14 are serially connected to each other. To the path P1, a path P2 (second path) is connected. The path P2 includes the inductor 20 and the FET 30, which are serially connected to each other. To be more detailed, an end of the inductor 20 is connected to a connection point N, and the drain (or source) of the FET 30 is connected to the other end of the inductor 20. The source (or drain) of the FET 30 is grounded.Type: GrantFiled: August 4, 2006Date of Patent: May 26, 2009Assignee: NEC Electronic CorporationInventor: Hiroshi Mizutani
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Patent number: 7538995Abstract: A semiconductor IC device includes an electrostatic protective circuit connected to an internal circuit connected between two pads. The internal circuit includes a matching circuit for adjusting the impedance between the two pads. The matching circuit includes n (n is a positive number of 2 or more) resistance elements connected in parallel between the two pads; n×m (m is a positive number of 2 or more) transistors, each m transistors connected in parallel being connected in series to the n resistance elements, respectively; and an adjustor for selectively allowing the transistors to perform an ON-operation. The resistance of each resistance element is set to a larger value than the impedance to be adjusted. Accordingly, a surge-current control effect is enhanced and breakdown of the transistors can be prevented.Type: GrantFiled: December 6, 2004Date of Patent: May 26, 2009Assignee: NEC Electronics CorporationInventor: Mototsugu Okushima
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Patent number: 7539847Abstract: A processor system that includes a main processor, and a coprocessor connected to the main processor. If the number of instruction execution cycles of an extended instruction executed by the coprocessor is larger than the number of instruction execution cycles of a basic instruction executed by the main processor, a pipeline process for a subsequent instruction retrieved after the extended instruction is stopped at least for a period corresponding to a difference between the number of instruction execution cycles of the extended instruction and the number of instruction execution cycles of the basic instruction.Type: GrantFiled: January 22, 2007Date of Patent: May 26, 2009Assignee: NEC Electronics CorporationInventor: Shinji Kashiwagi
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Patent number: 7537488Abstract: A connector of a communication cable includes a pair of power supply terminals disposed on a first surface inside a metal shield, a pair of signal terminals disposed on the first surface or a second surface different from the first surface inside the metal shield, and additional terminals for power supply or signal input/output. If the signal terminals are disposed on the first surface, the additional terminals are disposed on a surface different from the first surface. If the signal terminal is disposed on the second surface, the additional terminals are disposed on the first surface, the second surface, or a surface different from the first surface and the second surface.Type: GrantFiled: September 22, 2006Date of Patent: May 26, 2009Assignee: NEC Electronics CorporationInventor: Shunichi Iwakawa
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Patent number: 7537864Abstract: A method of designing hole patterns for arranging hole patterns on a pattern drawing of a photomask used during an exposure process in semiconductor integrated circuit manufacturing, wherein a grid is provided on the pattern drawing with a space smaller than a minimum pitch allowed by the design rule of the semiconductor integrated circuit, and the hole patterns are provided at lattice points, which are the intersections of the grid. Flexibility of hole pattern arrangement is improved and the quality of hole pattern arrangement can be easily evaluated.Type: GrantFiled: December 27, 2004Date of Patent: May 26, 2009Assignee: NEC Electronics CorporationInventors: Masashi Fujimoto, Seiji Matsuura
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Patent number: 7538022Abstract: The method of manufacturing an electronic circuit device according to an embodiment of the present invention includes preparing an interconnect substrate 10 including an interconnect 14 and an electrode pad 16 integrally formed with the interconnect 14; preparing an electronic circuit chip 20 including a solder electrode 22; and melting the solder electrode 22 and connecting it to the electrode pad 16, thus connecting the interconnect substrate 10 and the electronic circuit chip 20. A first metal material, exposed in the surface of the electrode pad 16 opposite to an insulating resin layer 12 and constituting the electrode pad 16, has higher free energy for forming an oxide than a second metal material exposed in the surface of the interconnect 14 opposite to the insulating resin layer 12 and constituting the interconnect 14.Type: GrantFiled: September 28, 2006Date of Patent: May 26, 2009Assignee: NEC Electronics CorporationInventors: Yoichiro Kurita, Koji Soejima, Masaya Kawano
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Patent number: 7538558Abstract: A failure detection apparatus for a semiconductor apparatus includes a clock line to transmit a clock signal, a shield line to shield the clock line, an inverted signal setting unit to supply signals inverted to each other to the clock and shield lines in a failure detection mode, and a failure detection evaluator to detect a failure by comparing static current consumption in each of the failure detection mode and a normal operation mode.Type: GrantFiled: March 23, 2007Date of Patent: May 26, 2009Assignee: NEC Electronics CorporationInventor: Hisashi Nakamura
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Patent number: 7538388Abstract: A semiconductor device has a semiconductor substrate, and a parallel p-n layer provided between the main surface and the back surface of the semiconductor substrate, and first-conductivity-type drift region and second-conductivity-type partition regions alternately arranged therein, wherein in the parallel p-n layer, the second-conductivity-type partition regions are periodically formed conforming to a basic periodicity specified by a predetermined distance, and SA/S (where, SA is a sectional area per a single second-conductivity-type partition region as viewed in a plane parallel with the main surface, and S is a sectional area of a unit structural region, periodically formed as containing one of the second-conductivity-type partition regions, as viewed in a plane parallel with the main surface) in an element-forming region allowing current to flow therethrough is smaller than SA/S in at least a portion of a periphery region surrounding the element-forming region.Type: GrantFiled: July 11, 2006Date of Patent: May 26, 2009Assignee: NEC Electronics CorporationInventors: Yoshinao Miura, Hitoshi Ninomiya
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Publication number: 20090128202Abstract: First and second counter circuits output a signal based on a trigger signal and a clock signal respectively. A selection circuit selects first to fourth signals as the trigger signal, the clock signal, the trigger signal and the clock signal. In a first output mode, an output circuit outputs signals exhibiting normal-phase and reversed-phase PWM waveforms based on both of the signals of the first and second counter circuits. In a second output mode, the output circuit outputs signals that are each based only on either of the signals of the first and second counter circuits.Type: ApplicationFiled: November 14, 2008Publication date: May 21, 2009Applicant: NEC Electronics CorporationInventor: Yasuhiro Takata
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Publication number: 20090127721Abstract: A semiconductor integrated circuit comprises a first and second common wiring layers common to a plurality of types of products and independent of a user circuit, a customized layer provided between the first common wiring layer and the second common wiring layer and which is configured to form the user circuit. The second common wiring layer is formed above an upper layer of the first common wiring layer, and an universal logic cell is wired to the first and second common wiring layers and the customized layer. A power supply wiring, which is connected to a power supply pad, which is connected to an external power supply, is formed through the second common wiring layer, and the power supply wiring is formed in the same layer as the power supply pad and extends to an internal circuit area in which the universal logic cell is formed.Type: ApplicationFiled: November 13, 2008Publication date: May 21, 2009Applicant: NEC Electronics CorporationInventor: Toshio ISONO
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Publication number: 20090128973Abstract: A protection ability of a power supply control circuit is improved so as to protect an output transistor against a back electromotive voltage from a load, a dump surge voltage, and a positive spike surge voltage which has a smaller energy but is higher than the dump surge voltage. The power supply control circuit includes: an output MOS transistor (power semiconductor device) connected between a first power supply terminal and an output terminal; a load connected to the output terminal; a first dynamic clamping circuit for controlling a voltage difference between a first power supply line and the output terminal; and a first switch connected between the first dynamic clamping circuit and the output MOS transistor, in which a conductive state is determined according to a result of comparison between a reference voltage and a voltage at the output terminal.Type: ApplicationFiled: October 28, 2008Publication date: May 21, 2009Applicant: NEC Electronics CorporationInventor: Akihiro Nakahara