Abstract: An edge section of a wafer can be polished, and at same time, a polishing surface of a polishing member can be dressed by a dresser mechanism. A polishing member has annular concave trenches, which are coaxially formed in the front surface thereof, and at least an inner surface of the concave trenches is composed of an inclined polishing surface for polishing an edge section of the wafer, and a wafer pressing mechanism presses the edge section of the wafer against the inner surfaces in at least one side of the concave trench of the polishing member, and a dresser mechanism dresses at least the inner surfaces in at least one side of the concave trench of the polishing member.

Abstract: A frequency dividing phase shift circuit includes a first frequency divider and a second frequency divider. The first frequency divider is configured to perform 1/(2n+1) (n is a natural number) frequency division on an input signal having a frequency of (freq*2(2n+1)) (“freq” indicates a frequency) to generate a first signal having a frequency of (freq*2). The second frequency divider is configured to perform ½ frequency division on the first signal to generate 4-phase signals which are different in phase by 90 degrees one after another.

Abstract: In a constant current source apparatus for supplying a load current to at least one load, first and second output terminals are provided, and at least one of the first and second output terminals is capable of being connected to the load. First and second depletion-type MOS transistors are connected in series between the first and second output terminals. A source and a gate of the first depletion-type MOS transistor are connected to a gate of the second depletion-type MOS transistor.

Abstract: A processor has an instruction set A and an instruction set B. A system instruction decoder decodes a system instruction that specifies the operating mode of the processor, the system instruction not being included in either the instruction set A or the instruction set B. A system instruction execution controller receives a decoded signal from the system instruction decoder, which has decoded an instruction requiring changeover of the instruction set, and sets the value of a instruction mode register. On the basis of the value in the instruction mode register, an instruction set changeover unit selects the instruction set to be used.

Abstract: A semiconductor chip and a wiring strip are placed on a flat side of a base sheet. The semiconductor chip has parallel first and second surfaces. Electrodes are connected to the first surface. The electrodes all terminate in the plane of the flat side of the base sheet and adhesively connected to the flat side of the base sheet. The wiring strip has one end portion connected to the second surface of the semiconductor chip and the opposite end portion terminating in the plane of the flat side of the base sheet and adhesively connected to the flat side of the base sheet. A mold resin fills gaps between the semiconductor chip, the wiring strip, and the base sheet to lock the semiconductor chip and the wiring strip. The base sheet is removed.

Abstract: A predetermined pattern containing a plurality of gate patterns, in the process of formation thereof, is classified into fine gate patterns and the other patterns (S102), and a hard mask film is formed on a process target film (S106). Next, a first resist film having a fine first pattern is formed on the hard mask film, and the hard mask film is then patterned (S108). Thereafter, a resist film having a separate pattern is formed on the hard mask film, and a process target film is selectively dry-etched through the hard mask film and the resist film used as masks (S110 and S112).

Abstract: To reduce the apparent effect of offset voltage by making the offset voltage spatially scattered.

Abstract: A designing method of a semiconductor device is achieved by setting interconnection reference data indicating permissible interconnection widths which are discrete, and a permissible interval between adjacent two of interconnections, the interconnection intervals being discrete; and by specifying an interconnection relating an impermissible width and interconnections relating to an impermissible interval from the interconnections for a semiconductor device based on the interconnection data. The permissible widths and the permissible intervals are preferably equal to or larger than a minimum design dimension.

Abstract: With the damascene process in which an interconnection is formed using a conventional chemically amplified positive photoresist composition, there arises a problem that the photoresist within the via hole (as well as in its vicinity) may remain even after the exposure and the development are carried out. The present invention relates to a chemically amplified resist composition comprising, at least, a photo acid generator, a quencher and a salt having a buffering function for an acid which is generated from the acid generator by irradiation, wherein the salt having the buffering function for the acid generated from the acid generator is a salt derived from a long chain alkylbenzenesulfonic acid or a long chain alkoxybenzenesulfonic acid and an organic amine that is a basic compound.

Abstract: The semiconductor device includes multilayer wirings of a dual damascene structure. The multilayer wirings include a first wiring layer formed on a semiconductor substrate and a second wiring layer formed on the first wiring layer. The first wiring layer includes a first insulation film, plural first vias provided in the first insulation film, a second insulation film provided on the first insulation film, and a first wiring provided on the first vias and connected to those first vias in the second insulation film. The second wiring layer includes a third insulation film, plural second vias provided in the third insulation film, an adhesive layer provided on the third insulation film, a fourth insulation film provided on the adhesive layer, and a second wiring provided on the second vias and connected to those second vias in the fourth insulation film.

Abstract: A semiconductor integrated circuit includes: an output pad from which an output signal is outputted; an output signal line connected with the output pad; a first pad configured to function as a ground terminal or a power supply terminal; a first wiring connected with the first pad; an output driver connected with the output pad and configured to generate the output signal; an ESD protection device connected with the output signal line and having a function to discharge surge applied to the output pad; and a first trigger MOS transistor used as a trigger device. The output driver includes: a first protection target device connected between the output signal line and the first interconnection; and a first resistance element connected between the first protection target device and the first interconnection.

Abstract: A semiconductor chip comprises a semiconductor substrate, a multi-layer wiring structure on the semiconductor substrate, a seal ring structure on the semiconductor substrate, and a semiconductor element arranged in an inner region of said semiconductor chip and in a frame region of said semiconductor chip. The semiconductor element comprises a chip internal circuit, the inner region is enclosed by the seal ling structure, and the seal ring structure separates the frame region as being outside of the inner region.

Abstract: A semiconductor device having improved adhesiveness between films composing an interlayer insulating film is presented by providing multilayered films in the interlayer insulating films having film density distribution, in which the film density is gradually changes. A SiOC film is deposited to a thickness of 300 nm via a plasma CVD process, in which a flow rate of trimethylsilane gas is stepwise increased. In this case, the film density of the deposited SiOC film is gradually decreased by stepwise increasing the flow rate of trimethylsilane gas. Since trimethylsilane contains methyl group, trimethylsilane has more bulky molecular structure in comparison with monosilane or the like. Thus, the film density is decreased by increasing the amount of trimethylsilane in the reactant gas.

Abstract: The switch circuit 1 includes a common terminal 10 (common port), a plurality of branch terminals 22, 24, a common path P0 connecting the common terminal 10 and a diverging point N, branch paths P1, P2 connecting the diverging point N and the branch terminals 22, 24 respectively, distributed constant FETs 32, 34 respectively provided in the branch paths P1, P2, and transmission lines 42, 44 provided between the diverging point N on the branch paths P1, P2 and the distributed constant FETs 32, 34 respectively. Here, the transmission lines 42, 44 are longer than 45% of ?/4 but shorter than ?/4, when ? designates a propagation wavelength under an operating frequency.

Abstract: A clock duty changing apparatus changes a duty ratio of an input clock signal with nearly 50% duty ratio to a target value being externally supplied and outputs the input clock signal thereinafter as an output signal. The apparatus includes a duty regulation circuit and a duty correction circuit. The duty regulation circuit includes a delay selection circuit and an operation circuit. The delay selection circuit generates a delay signal by delaying the input clock signal by delay time determined based on a first control signal and a second control signal. The first control signal is externally supplied to the apparatus. The second control signal is generated by the duty correction circuit so that mismatch between the duty ratio of the output clock signal and the target value is reduced. The operation circuit generates the output clock signal by logic operation using the delay signal and the input clock signal.

Abstract: A semiconductor integrated circuit device includes: a first bias generating circuit, a second bias generating circuit and a control circuit. The first bias generating circuit generates a first substrate bias voltage of a P-channel transistor. The second bias generating circuit generates a second substrate bias voltage of N-channel transistor. The control circuit controls the first bias generating circuit and the second bias generating circuit independently on the basis of operating states of circuits to which the first substrate bias voltage and the second substrate bias voltage are applied.

Abstract: A transient voltage occurring between output terminals during ON/OFF operation is reduced. There are provided a pair of input terminals IN1 and IN2, a pair of output terminals OUT1 and OUT2, MOSFETs N1 and N2 connected between the output terminals, and a drive circuit 10 connected between the input terminals IN1 and IN2 and the MOSFETs N1 and N2. A light-emitting diode D1 is connected between the input terminals IN1 and IN2. The MOSFETs N1 and N2 have their source electrodes electrically connected to each other and their drains connected to the output terminals OUT1 and OUT2 respectively. The drive circuit 10 includes a photodiode array FD1 that supplies a drive voltage to the gates of the MOSFETs N1 and N2, and a discharge circuit 11, connected between the gate electrodes and the source electrodes of the MOSFETs N1 and N2, that discharges electric charges accumulated on each gate electrode. (FIG.

Abstract: A semiconductor package includes an insulating substrate configured to be provided for mounting a semiconductor chip which processes a signal with a frequency in a radio frequency band. The insulating substrate includes a first external connecting electrode, a second external connecting electrode, and a partial antenna wiring. The first external connecting electrode and the second external connecting electrode are connected with the partial antenna wiring. Each of the first external connecting electrode and the second external connecting electrode is an electrode to be connected with an external antenna pattern.

Abstract: The semiconductor device has a semiconductor substrate; an electric fuse provided on the semiconductor substrate, and having a first fuse link and a second fuse link connected in series; and a terminal provided between the first fuse link and the second fuse link, wherein the first fuse link and the second fuse link are configured as being different from each other in current value necessary for blowing.

Abstract: A variation detection device has a processor, an AD converter converting a signal voltage output from a sensor to generate an AD converted value and outputting the AD converted value to the processor, a temperature sensor detecting a temperature of the sensor, and a memory storing a table which indicates a relationship between temperatures and initial values. When receiving the AD converted value, the processor identifies a temperature of the sensor based on an output of the temperature sensor, reads out an initial value corresponding to the identified temperature from the table, and calculates a variation between the initial value and the AD converted value.