Patents Assigned to NEC
  • Patent number: 7705437
    Abstract: Disclosed herewith is a semiconductor device, which includes a semiconductor chip; a lead device that includes an island for mounting the semiconductor chip and having an area smaller than that of the semiconductor chip at its contact surface, as well as plural hanging leads for supporting the island and coming in contact partially with the semiconductor chip; a mounting material provided on a contact surface between each of the island and hanging leads and the semiconductor chip so as to adhere the semiconductor chip to the island and the hanging leads; and sealing resin for sealing the semiconductor chip. The modulus of elasticity of the mounting material is lower than that of the sealing resin. The mounting material is further coated on the back surfaces of the contact surfaces of the island and the hanging leads.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: April 27, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Naoto Kimura
  • Patent number: 7706801
    Abstract: When a terminal is moved to an area covered by a different switching node RNC of a radio access network, degradation of speech quality is prevented by returning a transcoder insertion connection to a transcoder-free-operation connection. When the terminal is moved and the switching node RNC of the radio access network is changed, a relocation is performed by inserting the transcoder, re-confirmation of parameter information of a bandwidth-compression coding system is requested for a local side switching node RNC and a remote side switching node RNC and, when the transcoder can be bypassed according to the confirmation, the transcoder is removed to return to the transcoder-free-operation connection mode.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: April 27, 2010
    Assignee: NEC Corporation
    Inventor: Toshiyuki Tamura
  • Patent number: 7704877
    Abstract: When a multi-layer structure is formed by forming the interconnect trenches or via holes having different patterns in a plurality of insulating films, an anti-reflective film and an upper resist film are stacked in this order over an insulating interlayer, and the anti-reflective film is etched through the upper resist film used as a mask, wherein the anti-reflective film is etched while varying a value of at least one etching condition correlative to ?(L2?L1), expressing dimensional shift of width L2 of opening of the recess formed in the insulating film, with respect to width L1 of opening of the upper resist film, so as to reduce the dimensional shift ?(L2?L1) as the aperture ratio of the opening to be formed in the upper resist film increases, depending on the aperture ratio.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: April 27, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hidetaka Nambu
  • Patent number: 7706601
    Abstract: An object pose estimating and matching system is disclosed for estimating and matching the pose of an object highly accurately by establishing suitable weighting coefficients, against images of an object that has been captured under different conditions of pose, illumination. Pose candidate determining unit determines pose candidates for an object. Comparative image generating unit generates comparative images close to an input image depending on the pose candidates, based on the reference three-dimensional object models. Weighting coefficient converting unit determines a coordinate correspondence between the standard three-dimensional weighting coefficients and the reference three-dimensional object models, using the standard three-dimensional basic points and the reference three-dimensional basic points, and converts the standard three-dimensional weighting coefficients into two-dimensional weighting coefficients depending on the pose candidates.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: April 27, 2010
    Assignee: NEC Corporation
    Inventor: Masahiko Hamanaka
  • Patent number: 7707476
    Abstract: A device and a method that improve decoding characteristics of an LDPC decoder to which SPA where the equation for the computation of messages is approximated and the number of messages are reduced is applied. A received LDPC code is decoded by repeating the passing of messages between a plurality of check nodes and a plurality of bit nodes corresponding to a check matrix, and messages sent from one of the check nodes to one of the bit nodes out of messages sent from the one of bit nodes to the one of check nodes are weighted at the one of bit nodes so that the longer ago the messages are computed at the one of check nodes, the less influential they become.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: April 27, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Katsutoshi Seki
  • Patent number: 7706970
    Abstract: The present invention provides a passenger location information system that provides information on the current location of a user during a trip in real time and in a mode suitable for each user. A configuration is provided in which passenger location information, at least including information on the ends (station, stop, etc.) of a transportation line interval in which a portable information terminal is located, is output at a predetermined time on a user terminal 1 such as a mobile phone terminal connectable to a network. In addition, using notification means such as a ringing tone or a vibrator, the user terminal 1 notifies the user, under a condition set by the user in advance, that the user is approaching a destination to prevent the user from riding past a destination due to dozing.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: April 27, 2010
    Assignee: NEC Corporation
    Inventor: Yutaka Inoue
  • Patent number: 7705695
    Abstract: A composite via structure in a multilayer printed circuit board (PCB) and also compact and shielded filters formed by the use of composite via structures as building blocks are provided. The composite via structure consists of two functional parts. The first functional part is designed to form an interconnected circuit with low return and leakage losses between the first pad disposed at the one side of the PCB and the special pad serving for a connection to a planar transmission line. The second functional part of the composite via structure serves to form a shielded open- or short-circuited resonant length (stub) extended in the vertical direction from the special pad to the second pad disposed at the opposite side of the PCB.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: April 27, 2010
    Assignee: NEC Corporation
    Inventor: Taras Kushta
  • Patent number: 7707332
    Abstract: An I/O-request processing system which is capable of reducing the maximum value of the time required until the I/O request of each external device is registered. An I/O-request receiving section (501) receives an I/O request issued from an external device (600). A process-information storage section (510) stores an I/O-request delay time (512) for each external device (600). A priority-process judgment section (520) registers the I/O request having a maximum I/O-request delay time (512) among the I/O requests which have been registered into an I/O-request cue (540).
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: April 27, 2010
    Assignee: NEC Corporation
    Inventor: Masao Shimada
  • Patent number: 7705844
    Abstract: A three-dimensional image/two-dimensional image display device includes a plurality of display pixels, and a lenticular lens for three-dimensional display. Each display pixel is consisted of M×N number of sub-pixels to be viewed from N view points. A pitch a of sub-pixels arranged in the longitudinal direction of ridge projection of the lenticular lens and a pitch b of the sub-pixels arranged in a direction orthogonal to the longitudinal direction of the lenticular lens satisfy the following expression. The M×N number of sub-pixels included in each of said display pixels are formed within a square area.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: April 27, 2010
    Assignee: NEC Corporation
    Inventors: Shin-ichi Uehara, Naoyasu Ikeda, Nobuaki Takanashi
  • Patent number: 7705245
    Abstract: An electronic device substrate is formed of a thin-plate reinforcing substrate; an external connection wiring layer stacked on the reinforcing substrate, and comprising an electrical insulation provided on the reinforcing substrate, an opening formed in the electrical insulation, a first conductor pattern and a via-hole conductor provided in the opening and formed integrally with each other; and a second conductor pattern formed on the opposite side of the electrical insulation to the reinforcing substrate, and at least partially electrically connected to the via-hole conductor.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: April 27, 2010
    Assignees: Hitachi Cable, Ltd., NEC Electronics Corporation
    Inventors: Nobuaki Miyamoto, Akira Chinda, Koki Hirasawa, Kenji Uchida
  • Patent number: 7705422
    Abstract: A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: April 27, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Masayuki Furumiya, Kuniko Kikuta, Ryota Yamamoto, Makoto Nakayama
  • Patent number: 7706287
    Abstract: The present invention provides an optimum ADSL line configuration parameter to a subscriber line and improves performance quality of an ADSL line. An ADSL line performance test portion implements an ADSL performance test before starting ADSL line service operation and grasps a subscriber line state. Test results are stored in a database and are referred to for the sake of maintenance of ADSL line service. In addition, the ADSL line performance test portion operates in a maintenance mode as required and also implements the ADSL line performance test in an ADSL line service operation state so as to constantly hold in the database a current optimum ADSL line configuration parameter for the subscriber line.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: April 27, 2010
    Assignee: NEC Corporation
    Inventor: Masashi Tanaka
  • Patent number: 7705408
    Abstract: A MOSFET has a base layer and a source layer in a cell surrounded by a trench gate formed in a semiconductor substrate. A trench contact is formed through the source layer and the base layer. The gate is polygonal such as square. The trench contact is thin and linear so as to increase embedding characteristics. Further, the trench contact is ring or cross shaped so as to reduce a source length.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: April 27, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hideo Yamamoto, Kenya Kobayashi
  • Patent number: 7704827
    Abstract: An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate trench and a polysilicon is formed in the gate trench with the gate insulator interposed therebetween. An HTO film is formed on the surface of the polysilicon and the n? epitaxial layer. At this time, an ion plantation is performed to the epitaxial layer through the HTO film. Hence, a p diffused base layer, an n+ diffused source layer, an n+ diffused source layer is formed. A CVD oxide film is formed on the HTO film. After a BPSG having flowability is deposited on the CVD oxide film, the BPSG film is planarized with a heat treatment of 900-1100 degree Celsius.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: April 27, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Yoshimitsu Murase, Kenya Kobayashi, Hideo Yamamoto, Atsushi Kaneko
  • Patent number: 7706762
    Abstract: An objective of this invention is to obtain a signal processing circuit and a signal processing method that reduce temperature-induced distortion when inputting a signal to a mixer and changing the frequency of the signal to a desired frequency. If a sensing result from a temperature sensor 133 is lower than a predetermined temperature, the attenuation factor of a first variable attenuator 102 is large while the attenuation factor of a second variable attenuator 108 is small. The magnitude relationship between the attenuation factors is reversed in a temperature range of the predetermined temperature or more. In a mixer 104 in which at a low temperature, the gain increases, and distortion increases, an increase in IM3 distortion can be prevented by increasing the attenuation factor at a low temperature. The same applies to a case where a mixer that has an amplifier arranged at a preceding stage thereof and makes the amplification factor of the amplifier large at a low temperature is used.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: April 27, 2010
    Assignee: NEC Corporation
    Inventor: Akihiro Kirisawa
  • Patent number: 7707370
    Abstract: An information processing device is provided with a plurality of memory channels, and performs interleave control on a unit memory connected to a memory channel. Furthermore, the information processing device has a circuit for performing the interleave control such that an interleave number on access to the unit memory connected to the memory channel can be constantly a multiplier of 2.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: April 27, 2010
    Assignee: NEC Corporation
    Inventor: Norihiko Inoue
  • Patent number: 7705953
    Abstract: Disclosed is a display device including: a display panel on which a plurality of driver chips are mounted by using a COG configuration; a signal substrate on which a timing controller for generating a differential signal inputted into each of the driver chips is formed; and a connecting substrate which connects the plurality of driver chips with the timing controller, wherein the connecting substrate includes a first connecting substrate on which a first line for inputting the differential signal into a driver chip excluding a driver chip located at a terminating area is formed and a second connecting substrate on which a second line for inputting the differential signal into the driver chip located at the terminating area, and wherein a termination resistor connects the second line for transmitting the differential signal which is formed on the second connecting substrate.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: April 27, 2010
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Setsuko Sato
  • Patent number: 7705799
    Abstract: Provided is an electronic device including: a device main body that processes data; a display device arranged in the device main body to display the data; a first operation device arranged in the device main body on a display surface side of the display device within a movable range of fingers of a hand for holding the device main body; a second operation device arranged in the device main body on an opposite side of the display surface within the movable range of the fingers of the hand for holding the device main body; and a control circuit that causes, only when one of the first operation device and the second operation device is being operated, the other to function.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: April 27, 2010
    Assignee: NEC Corporation
    Inventor: Souhei Niwa
  • Patent number: 7705937
    Abstract: An IPS-mode transflective LCD device includes an array of pixels each including a reflective region and a transmissive region juxtaposed. The reflective region operates in a normally-white mode, and the transmissive region operates in a normally-black mode. A common data signal is supplied to the reflective region and transmissive region, whereas the common electrode signal in the transmissive region is an inverted signal of the common electrode signal in the reflective region, to thereby obtain similar gray-scale levels.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: April 27, 2010
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Michiaki Sakamoto, Jin Matsushima, Hiroshi Nagai, Kenichi Mori, Hidenori Ikeno, Yasuki Kudo, Ken Sumiyoshi
  • Publication number: 20100100511
    Abstract: To detect a statistical change-point that appears in time-series data with a high accuracy. A first model learning section 102 learns the occurrence probability distribution of time-series data 111 as a first statistical model (for example, a latent Markov model) defined by a finite number of variables including a latent variable. In the subsequent processing, the degree of a temporal change in the probability distribution is computed for each of the probability distribution of the entire first statistical model, its partial probability distribution (the probability distribution of the latent variable and conditional probability distribution contingent on the value of the latent variable), and the probability distribution in which the above plural probability distributions are linearly-combined with a weight. The change-point of the time-series data 111 is detected on the basis of the computed degree of the change.
    Type: Application
    Filed: January 16, 2008
    Publication date: April 22, 2010
    Applicant: NEC Corporation
    Inventors: Shunsuke Hirose, Kenji Yamanishi