Abstract: A semiconductor integrated circuit having an internal circuit which is tested based on a scanning method is provided. The internal circuit has: memory elements including a first memory element and a second memory element; combinational circuits including a first combinational circuit receiving an external input data, a second combinational circuit outputting an external output data and a third combinational circuit; a first selection circuit; and a second selection circuit. The first selection circuit receives the external input data and a stored data held by the first memory element, and outputs any of them to the first combinational circuit. The second selection circuit receives the external output data output from the second combinational circuit and an operation result data output from the third combinational circuit, and outputs any of them to the second memory element.

Abstract: A storage device, a data arrangement method and a computer program are disclosed, in which the redundancy is maintained even if a cache module runs out of order, and the deterioration of the write processing performance is prevented at the time of failure of the cache memory module. When cache 0 fails while cache 0 and cache 1 possess duplicate data that is not stored in disks, data of cache 0 is copied onto data of cache 4 that is synchronized with the disks.

Abstract: A power amplifier circuit includes a first variable gain amplifier for amplifying an input signal, a second variable gain amplifier for amplifying an output signal of the first amplifier, and a control circuit for controlling the gain of the first variable gain amplifier based on the output signal of the first variable gain amplifier and the gain of the second variable gain amplifier.

Abstract: A liquid crystal display control circuit comprising a counter, inputted with a first signal for controlling a display status of a display unit and a second signal corresponding to an image data to be displayed on the display unit, for counting clocks for the second signal in 1 cycle of the first signal and for outputting the count value, a latch circuit for latching the number of clocks for the second signal included in 1 cycle of the first signal and for outputting the number of CLKs in 1 cycle, a reference count value circuit for generating a reference count value according to the number of CLKs in 1 cycle, and a comparator for generating a driver control signal that changes a current capacity of the driver unit according to the reference count value and the count value.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: An object collation method comprising a registration procedure for registering the registered data of a registered object in a database, and a collation procedure for collating the input image of a target object with the registered data. The registration procedure includes a step of storing the three-dimensional shape of the registered object and a texture space defined by a texture group indicating the luminance and/or color information of each position of the object surface under various illumination conditions. The collation procedure includes the steps of: generating an illumination fluctuation space defined by the image group under the various illumination conditions, at the location and position of the target object in the input image from the three-dimensional shape and the texture space; and collating the target object and the registered object based on the distance between the illumination fluctuation space and the input image.

Abstract: A balun circuit includes a first CPW line 11, a second CPW line 12a, and a third CPW line 12b that serve as signal input/output ports; a first CPS line 14a that is a differential transmission line, the first CPS line 14a relaying the first CPW line 11 to the second CPW line 12a; a second CPS line 14b that is a differential transmission line, the second CPS line 14b relaying the first CPW line 11 to the third CPW line 12b; and at least one connection section that connects grounded conductors of each of the first CPW line 11, the second CPW line 12a, and the third CPW line 12b.

Abstract: Provided is an optical head device and an optical information recording or reproducing device for performing recording or reproduction to/from a plurality of types of optical recording medium, which can obtain a stable track error signal by a small size and exhibits high efficiency. Light PD and light PC emitted from a double-wavelength light source make incidence to a diffractive optical element in the same polarization directions. Diffraction gratings have a double refractive characteristic and in these areas the polarization directions of the two light beams become orthogonal. The light of 650 nm band is divided into 0th-order light and ±1st-order diffracted light in one of the diffraction grating and transmits through the other diffraction grating. The light of 780 nm band transmits through one of the diffraction grating and is divided into 0th-order light and ±1st-order diffracted light in the other diffraction grating.

Abstract: A thermistor device having a high-speed response to temperature and a large ON/OFF ratio at the operating temperature. The thermistor device comprises a first layer of a first material having a positive temperature coefficient of resistance and a second layer of a second material having a semiconductivity and formed directly on the first layer. As the first material changes from conductive to a semiconductive or an insulative at or near the transition temperature TM-I, the interface between the first and second layer changes to a pn junction.

Abstract: The present invention provides a semiconductor device exhibiting an improved reliability of a bump coupling section. A semiconductor device is provided, which comprises: an interconnect layer; a stress-relaxing layer, covering the interconnect layer and provided with an opening exposing at least a portion of the interconnect layer; a post, covering the opening and provided so as to overlap with the stress-relaxing layer disposed around the opening; and a resin layer, provided around the post to cover the stress-relaxing layer, wherein a value of 2A/C is within a range of from 0.1 to 0.5, wherein C is a diameter of the post and 2A is a width of an overlapping region of the stress-relaxing layer with the post.

Abstract: A semiconductor device includes circuits to be tested, an input terminal for receiving a tester clock signal from outside, a built-in self-test (BIST) circuit for logically testing the circuit at every cycle of a tester clock signal, and an output terminal for outputting a test result signal representing a result of testing performed in the BIST circuit. Before generating a test result signal, the BIST circuit generates a marker signal, whose phase is identical to the phase of the test result signal, instead of the test result signal.

Abstract: A trench is formed by a process which removes a damage layer formed on a sidewall of a low dielectric constant layer, a process which forms a second protection insulating layer by a chemical vapor deposition (CVD) technique and forms a second concave portion by covering a sidewall of the low dielectric constant layer with the second protection insulating layer, and a process which shapes the second protection insulating layer by etch back so that a trench has a sidewall that the second protection insulating layer is selectively formed on a surface of the low dielectric constant layer.

Abstract: A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, and a Y-switch circuit that is arranged for each of the bit line pairs and is configured to select each of the bit line pairs. The semiconductor memory device further includes a mode switching unit that switches the normal mode and the test mode in accordance with a mode selection signal that is externally supplied, a plurality of individual control units that control operation of each of the precharge circuits in accordance with operation of each of the Y-switch circuits in the normal mode, and a block control unit that collectively turns off all of the precharge circuits in the test mode.

Abstract: A semiconductor device including a substrate, a semiconductor chip mounted on the substrate, and an encapsulation resin encapsulating the semiconductor chip, wherein the encapsulation resin contains a first resin region composed of a first resin composition, a second resin region composed of a second resin composition, and a mixed layer formed between the first resin region and the second resin region so as to have the first resin composition and the second resin composition mixed therein is provided.

Abstract: Provided is a communication system capable of fundamentally preventing an attack from an unspecified counterpart and resolve problem even when a problem occurs in a user terminal or client and a server. A mediation server (1) receives an attack from an outside source on behalf of a server (34) (server A), redirects and receives communication addressed to a node-representative ID, and performs first authentication for the communication. In the case of a reliable user terminal or client (42) (client B), the mediation server (1) provides the device with an intermediary server ID specifying an intermediary server (2). The intermediary server (2) performs second authentication for the user terminal or client (42) (client B) going through the mediation server (1).

Abstract: A designing apparatus includes an initial estimating portion, a general power supply noise analyzing portion, a layout designing portion, a detail estimating portion, a detail power supply noise analyzing portion, and a layout adjusting portion. The initial estimating portion estimates general values of an entire consumed current and an entire on-chip capacitance. Based on the estimated general values, the general power supply noise analyzing portion creates a lumped constant circuit model so as to conduct a power supply noise analysis, for computing a current-capacitance ratio. Based on the current-capacitance ratio, the layout designing portion performs placement of cells for each of predetermined regions obtained by dividing a placement region. The detail estimating portion creates a lumped constant circuit model for each of the predetermined regions so as to estimate detail values of the consumed current and the on-chip capacitance for each of the predetermined regions.

Abstract: A voice recognition system comprises: a voice input unit that receives an input signal from a voice input element and output it; a voice detection unit that detects an utterance segment in the input signal; a voice recognition unit that performs voice recognition for the utterance segment; and a control unit that outputs a control signal to at least one of the voice input unit and the voice detection unit and suppresses a detection frequency if the detection frequency satisfies a predetermined condition.

Abstract: It is an object of the present invention to reduce output of a WAIT signal to maintain data consistency to effectively process subsequent memory access when there is no subsequent memory access in case of miss hit in a cache memory having a multi-stage pipeline structure. A cache memory according to the present invention performs update processing of a tag memory and a data memory and decides whether or not there is a subsequent memory access upon decision by a hit decision unit that an input address is a miss hit. Upon decision that there is a subsequent memory access, a controller outputs a WAIT signal to generate a pipeline stall for the pipeline processing of the processor to the processor, while the controller does not output a WAIT signal upon decision that there is no subsequent memory access.

Abstract: A substrate device includes: a substrate; a ground layer disposed on one of two opposing surfaces of the substrate; a transmission line disposed on the other of the two opposing surfaces of the substrate; a pad which is disposed on the other of the two opposing surfaces of the substrate and connected to the transmission line; and a connector connected to the pad via a contact point. The pad has a part on the transmission line side and a part positioned on the opposite side of the transmission line with respect to the contact point with the connector which are electrically insulated from each other.

Abstract: A marker generating system is characterized in having a special feature extracting element that extracts a portion, as a special feature, including a distinctive pattern in a video image not including a marker; a unique special feature selecting element that, based on the extracted special feature, selects a special feature of an image, as a unique special feature, that does not appear on the video image; and a marker generating element that generates a marker based on the unique special feature.