Patents Assigned to NEC
  • Patent number: 7680506
    Abstract: The object of the present invention is to realize a method and a server which enable insertion of advertisement even in voice communication including multimedia communication. The server is configured as a server for managing PoC communication among multiple terminals, comprising: a right-to-speak management section for managing the right to speak of the multiple terminals; a data distribution section for transmitting and receiving data to and from the multiple terminals; and an advertisement control section for storing advertisement data and transmitting the stored advertisement data to the multiple terminals via the data distribution section.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: March 16, 2010
    Assignee: NEC Corporation
    Inventors: Kazuhiro Takahashi, Yoshihiro Ono, Shin Harada, Takashi Shiraki, Takehiko Kashiwagi, Junpei Kamimura
  • Patent number: 7680299
    Abstract: In masquerading determination processing, a masquerading determination unit reads image data representing an image of an identification target on which a striped pattern is projected from an image storage unit to extract the striped pattern appearing in a face region of the image represented by the read image data. Subsequently, the masquerading determination unit determines whether a stripe in the face region in the image is a straight line or not. When the stripe is a straight line, because the identification target is a plane object such as a photograph or an image display device so that it can be determined that the target is at least not a person himself, the masquerading determination unit determines that the target masquerades. On the other hand, unless the stripe is a straight line, because the identification target has a solid configuration having three-dimensional irregularities to have a possibility of being a person himself, the unit determines that the target might not masquerade.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: March 16, 2010
    Assignee: NEC Corporation
    Inventor: Toshinori Hosoi
  • Patent number: 7679191
    Abstract: The semiconductor device, in which a flaking of a layer or an element is prevented, is provided. A bonding pad section 13 of a semiconductor device 1 includes a polysilicon film 131, a barrier metal film 133 provided on the polysilicon film 131 and a metallic electrode 134 provided on the barrier metal film 133. The surface roughness of the surface of the polysilicon film 131 in the side of the barrier metal film 133 is equal to or larger than 3 nm. Further, the polysilicon film 131 contains substantially no phosphorus.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: March 16, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kouji Nakajima
  • Patent number: 7681167
    Abstract: A judgment section determines whether or not a reduction in the power dissipation is possible by relocation of an improvement-target cell. If a reduction in the power dissipation is possible, a calculation section calculates the delay time of a target path including the improvement-target cell to obtain a possible shift distance of the improvement-target cell, within which the timing constraint is satisfied. A layout change section relocates the improvement-target cell within a range in which the power dissipation can be reduced and timing constraint can be satisfied.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: March 16, 2010
    Assignee: NEC Corporation
    Inventor: Takashi Goto
  • Patent number: 7679619
    Abstract: A data outputting method is provided which is capable of reducing a memory capacity of a LUT (Look-Up Table). Compressed data obtained by dropping low-order bits making up gray-level data is stored in a manner in which the compressed data can be accessed by high-order bits to be input to the LUT. High-order bits making up an address output from an address supplying unit are supplied to the LUT and low-order bits are supplied to a computing unit. The LUT outputs compressed gray-level data corresponding to the high-order bits and compressed gray-level data corresponding to data of (high-order bit+1). The computing unit outputs each of expanded gray-level data obtained by dividing data obtained by interpolation among one expanded gray-level data, another expanded gray-level data and, third expanded data for every high-order bit based on one compressed data, other compressed data, and lower-bits.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: March 16, 2010
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Kouichi Ooga, Tsuyoshi Ichiraku
  • Patent number: 7679559
    Abstract: A wide-angle null-fill antenna with no null in the depression angle range, an omni antenna using the same, and radio communication equipment. A null-fill antenna comprises a first antenna array including antenna elements arranged with a prescribed point as the center, and a second antenna array having amplitude characteristics substantially equal to those of the antenna elements forming the first antenna array. The first antenna array is excited so that the excitation amplitude distribution is to have symmetry with respect to the prescribed point, while the excitation phase distribution is to have point symmetry with respect to the prescribed point. The phase center of the first antenna array is substantially coincident with that of the second antenna array.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: March 16, 2010
    Assignee: NEC Corporation
    Inventor: Norihiko Oomuro
  • Patent number: 7679871
    Abstract: A semiconductor device includes a semiconductor substrate, a fuse which comprises a conductive material and is formed on a semiconductor substrate, a contacting target conductor region which is placed around the fuse on the semiconductor substrate and formed so as to make electrical contact with the fuse through the conductive material constituting the fuse when a process for cutting the fuse is carried out, and a determination unit which detects whether or not the fuse is electrically disconnected, and detects whether or not the contacting target conductor region and the fuse are electrically connected, and determines that the fuse is in a cut state when electrical disconnection of said fuse is detected or electrical connection between said contacting target conductor region and said fuse is detected.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: March 16, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Norio Okada, Takehiro Ueda
  • Patent number: 7681096
    Abstract: A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: March 16, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Tomonori Sasaki, Toshiharu Asaka, Yoshiyuki Nakamura
  • Patent number: 7679482
    Abstract: An inductor includes a first magnetic substance core which has a middle leg, a first outer leg, a second outer leg, and a body portion interconnecting the middle leg, the first outer leg and the second outer leg, and a second magnetic substance core which is arranged to be opposed to the first magnetic substance core. A first conductor is arranged in a first space which is formed by the middle leg, the first outer leg, part of the body portion, and the second magnetic substance core. A second conductor is arranged in a second space which is formed by the middle leg, the second outer leg, part of the body portion, and the second magnetic substance core. The middle leg is formed with a region which is lower in height than the first outer leg, in the same direction as the longitudinal direction of the first outer leg.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: March 16, 2010
    Assignee: NEC Tokin Corporation
    Inventors: Seiichi Yamada, Okikuni Takahata, Hiroyuki Kamata, Fumishirou Tsuda, Masahiro Kondo
  • Patent number: 7680214
    Abstract: A device (20) for computing a threshold Sthi used in demodulating a quadrature amplitude modulated (QAM) signal to generate a plurality of soft bits per received symbol for input to a turbo decoder, the device including: means (30) for computing the mean amplitude A of the received symbols and multiplying the mean amplitude A by of the received symbols and multiplying the mean amplitude A by a constant Ci for a square QAM constellation with 4m points, such that Sthi=A×Ci where m is a positive integer and i is a positive integer from 1 to (?4m-1)?1.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: March 16, 2010
    Assignee: NEC Corporation
    Inventor: Thanh Ngoc Bui
  • Patent number: 7678454
    Abstract: In a formation method for forming a fine structure in a workpiece (30) containing an etching control component, using an isotropic etching process, a mask (32, 34) having an opening (36) is applied to the workpiece, and the workpiece is etched with an etching solution (38) to thereby form a recess (40), corresponding to a shape of the opening, in a surface of the workpiece. The etching of the workpiece is stopped due to the etching control component eluted out of the workpiece in the etching solution within the recess during the isotropic etching process.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: March 16, 2010
    Assignee: NEC Corporation
    Inventors: Shin-Ichi Uehara, Yuko Sato, Ken Sumiyoshi, Setsuo Kaneko, Jin Matsushima
  • Patent number: 7680815
    Abstract: A user data management apparatus for connection to a terminal data processor used by a user through a network, registers data that is dependent on a user ID peculiar to the user. The user data management apparatus has a first unit for generating a first data registration screen, when data of the user is to be initially registered, which differs from user ID to user ID, and a second unit for displaying, on the terminal data processor, a second data registration screen based on the first data registration screen generated by the first unit, when the data of the user is to be registered.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: March 16, 2010
    Assignee: NEC Nexsolutions, Ltd.
    Inventors: Hikaru Komine, Katsuhiko Nakanishi
  • Patent number: 7680669
    Abstract: A plurality of sets of position code books indicating the pulse position are provided in a multi-set position code book storing circuit (450). In accordance with a pitch prediction signal obtained in an adaptive code book circuit (500), one type of position code book is selected from the plurality of position code books in a position code book selecting circuit (510). From the selected position code book, a position is selected by a sound source quantization circuit (350) so as to minimize distortion of a sound signal. An output of the adaptive code book circuit (500) and an output of the sound source quantization circuit (350) are transferred. Thus, a sound signal can be encoded while suppressing deterioration of the sound quality with a small amount of calculations even when the encoding bit rate is low.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: March 16, 2010
    Assignee: NEC Corporation
    Inventor: Kazunori Ozawa
  • Publication number: 20100059661
    Abstract: A relay circuit that includes: a light emitting element that outputs an optical signal in accordance with an input electric signal; a photoelectric conversion element that converts the optical signal into an electric signal and generates a potential difference between its opposite ends; a switching element that has a prescribed threshold value and that determines an output state in accordance with the potential difference that is generated by the photoelectric conversion element and that exceeds the prescribed value; first and second paths that are respectively connected to the opposite ends of the photoelectric conversion element and that transmit the potential difference generated by the photoelectric conversion element to the switching element; a discharge circuit that electrically connects the first path and the second path to each other when the potential difference generated by the photoelectric conversion element drops to a prescribed value; and a first resistor element that is arranged between the dis
    Type: Application
    Filed: August 12, 2009
    Publication date: March 11, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Tomohiro Minagawa
  • Publication number: 20100063795
    Abstract: [PROBLEMS] To provide a data processing device such as a text mining device capable of extracting characteristic structures properly even in case a plurality of words indicating identical contents or a plurality of words semantically associated are contained in input data. [MEANS FOR SOLVING PROBLEMS] Association node extraction unit (22) of a text mining device (10) extracts association nodes containing semantically associated words from a graph obtained as a result of syntax analysis. Association node joint unit (23) transforms the graph by joint of a part of or a whole of the association nodes. Characteristic structure extraction unit (24) extracts a characteristic structure from the graph transformed by the association node joint unit.
    Type: Application
    Filed: August 2, 2006
    Publication date: March 11, 2010
    Applicant: NEC CORPORATION
    Inventors: Yousuke SAKAO, Takahiro IKEDA, Yoshihiro IKEDA, Kenji SATOH
  • Publication number: 20100060354
    Abstract: The present invention is aimed at realizing an amplifying circuit whose chip size is prevented from being significantly increased even if the number of compatible frequencies increases, and which has a wide dynamic range when it operates under a low voltage.
    Type: Application
    Filed: April 24, 2007
    Publication date: March 11, 2010
    Applicant: NEC Corporation
    Inventor: Tadashi Maeda
  • Publication number: 20100061217
    Abstract: Semiconductor lasers emit lights having wavelengths of about 400 nm, 650 nm, and 780 nm, respectively. A transmittance adjustment element is provided in an optical path of the light reflected from a disk. The transmittance adjustment element includes a first optical thin film that changes transmittance of a 650-nm-wavelength light relatively to transmittance of 400-nm- and 780-nm-wavelength lights, and a second optical thin film that changes transmittance of a 780-nm-wavelength light relatively to transmittance of 400-nm- and 650-nm-wavelength lights. The transmittance adjustment element has the function of maintaining constant the intensity of light incident onto a photodetector irrespective of the type of medium.
    Type: Application
    Filed: November 30, 2007
    Publication date: March 11, 2010
    Applicant: NEC CORPORATION
    Inventor: Ryuichi Katayama
  • Publication number: 20100064272
    Abstract: In a layout design method of a semiconductor integrated circuit, an IR drop data is calculated to indicate a voltage drop for every local area, and a virtual arrangement library is generated which stores data of a circuit cell to be arranged based on the IR drop data for every circuit module. A virtual arrangement net list is generated by converting the circuit cell contained in a net list into a virtual arrangement cell which is registered on the virtual arrangement library. The circuit module is automatically arranged based on the virtual arrangement net list; and the virtual arrangement cell contained in the automatically arranged circuit module is replaced with the circuit cell contained in the net list.
    Type: Application
    Filed: September 3, 2009
    Publication date: March 11, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Kazunori Higashi
  • Publication number: 20100060323
    Abstract: A test circuit with which the cost for checking the duty ratio of a clock signal is restrained. A sampling timing generating circuit, to which the measurement-target clock signal MCK is input, outputs first and second sampling trigger signals to A sample-and-hold circuit 102 respective prescribed timings before and after a timing that is one-half period of the measurement-target clock signal after a first edge of the measurement-target clock signal. The sample-and-hold circuit samples and holds the measurement-target clock signal in correspondence with respective ones of the first and second sampling trigger signals. The sample-and-hold circuit forms all or part of a scan path and outputs a signal, which is being held for checking the duty ratio, from a scan output terminal in response to a scan clock signal.
    Type: Application
    Filed: September 3, 2009
    Publication date: March 11, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Yoshikazu Sumi
  • Publication number: 20100064267
    Abstract: A semiconductor device design support apparatus for generating a substrate netlist so as to be able to perform substrate noise analysis with high accuracy in a short time. The semiconductor device design support apparatus comprises a unit that divides a semiconductor device layout into a plurality of segments and generates a macro-model of the segments by using a current waveform of an instance included in the divided segments; a unit that replaces a pattern (termed as “substrate interface”) that is designed to be an interface with a substrate with respect to the segments, by a prescribed substrate interface diagram; and a unit that generates a substrate netlist, based on the substrate interface diagram of the plurality of segments.
    Type: Application
    Filed: September 3, 2009
    Publication date: March 11, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Mikiko Tanaka