Abstract: A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapted to generate an error indication according to whether the data value includes an error. An error storage circuit is couple to receive the error indication from the error detection circuit and is adapted to store an error address that corresponds to the selected storage location if the error indication indicates that the data value includes an error and if the error address is not already stored within the error storage circuit.

Abstract: A method and apparatus for using a binary CAM array to implement Classless Interdomain Routing (CIDR) address processing. A binary CAM array is segmented into a plurality of array groups, each of which includes a number of rows of binary CAM cells and an associated group global mask. Each array group may be assigned to a particular prefix length by storing a prefix mask pattern corresponding to the prefix length in the array group's associated group global mask. CIDR address entries are then stored in array groups assigned to corresponding CIDR prefixes so that an array group assigned to a particular prefix stores only CIDR addresses having that prefix.

Abstract: A bit line control circuit is coupled between a bit line of an associated Content Addressable Memory (CAM). Array and a supply voltage. The bit line control circuit adjusts the charge current for the bit line in response to a bit line control signal. For some embodiments, the bit line control circuit includes a dynamic component and a static component to control the bit line.

Abstract: A content addressable memory (CAM) device having a cascaded CAM array. The cascaded CAM array includes a first array of CAM cells and a second array of CAM cells. A first plurality of compare signal lines is coupled to the first array CAM cells and a second plurality of compare signal lines coupled to the second array of CAM cells. A plurality of storage elements have inputs coupled to the first plurality of compare signal lines and outputs coupled to the second plurality of compare signal lines.

Abstract: A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a corresponding CAM cell in each of the plurality of rows of CAM cells, a plurality of timed storage circuits, each having a data input coupled to a corresponding match line and having an enable input coupled to an enable signal line, a timing generator configured to generate an enable signal on the enable signal line, and a plurality of load elements.

Abstract: A method and apparatus for determining a longest prefix match in a content addressable memory (CAM) device is described. The CAM device includes a CAM array that may be arbitrarily loaded with CIDR addresses that are not prearranged prior to their entry into the CAM device. For one embodiment, the CAM array is a ternary CAM array that includes CAM cells storing CAM data, mask cells storing prefix mask data for the corresponding CAM cells, a CAM match line for indicating a match between a search key and the CAM data (as masked by the prefix mask data), prefix match lines, and prefix logic circuits for comparing the CAM match line with the prefix mask data. The prefix logic circuits determine the longest prefix among the CAM locations that match the search key, regardless of where the matching locations are logically located in the CAM array.

Abstract: A content addressable memory device including a memory to store a searchable database, a search circuit, and a first-in-first-out storage circuit. The search circuit generates a plurality of address values that correspond to unoccupied storage locations within the memory, and the plurality of address values are queued within the first-in-first-out storage circuit to enable the address values to be read in succession by an external device.

Abstract: A content addressable memory (CAM) cell including a memory cell coupled to a word line, a compare circuit coupled to the memory cell and to a match line, and a driver circuit having an input coupled to the match line and an output coupled to the word line.

Abstract: An apparatus including a content addressable memory (CAM) array, a clocked circuit coupled to the CAM array, and a programmable delay circuit coupled to receive a reference clock signal and generate a programmable delayed clock signal using a delay element for the clocked circuit. The CAM array may include a plurality of rows of CAM cells each having a corresponding match line for carrying a match signal indicative of whether comparand data matches data of the corresponding row of CAM cells.

Abstract: A monolithic Multi-chip Module (MCM) package includes two or more individual CAM dice mounted on a substrate formed as, for example, a plastic ball grid array (PBGA) package. The substrate includes an interconnect structure to route signals between corresponding pads of the CAM dice and balls of the MCM package. In some embodiments, the footprint of the MCM ball grid array package is identical to the footprint of a similar PBGA package housing a single CAM die. Each CAM die within the MCM package may be assigned the same device identification number (DID).

Abstract: A content addressable memory (CAM) has a main array including a plurality of rows of CAM cells, one or more spare rows of CAM cells selectable to functionally replace defective rows of CAM cells in the main array, and a control circuit for disabling the defective rows by writing predetermined data to the defective rows of CAM cells.

Abstract: A method and apparatus for simultaneously performing a plurality of compare operations in a content addressable memory (CAM) device. For one embodiment, the CAM device includes first and second memory cells to store first and second data, and first and second compare circuits coupled respectively to first and second match lines. The first compare circuit has a first input coupled to the first memory cell, a plurality of second inputs to receive first comparand data, and a third input coupled to the second memory cell. The second compare circuit has a first input coupled to the first memory cell, a plurality of second inputs to receive second comparand data; and a third input coupled to the second memory cell.

Abstract: A content addressable memory (CAM) cell includes a memory cell storing data values. The memory cell includes a surrounding-gate thyristor and an access transistor. The CAM cell also includes a compare circuit coupled among the memory cell and a match line. The compare circuit receives data and comparand data and affects a logical state of a match line in response to a predetermined relationship between the data and comparand data. The compare circuit includes a first transistor set coupled for conduction state control by signals representative of the data, and a second transistor set coupled for conduction state control by signals representative of the comparand data.

Abstract: A word line driver circuit is coupled to a word line of an associated Content Addressable Memory (CAM) array. The word line driver circuit adjusts the word line read voltage in response to a compare signal indicative of whether the CAM array is performing a concurrent compare operation. For some embodiments, the word line driver circuit selectively provides a relatively high word line read voltage or a relatively low word line read voltage in response to the compare signal.

Abstract: A content addressable memory (CAM) device having a cascaded CAM array. The cascaded CAM array includes a first array of CAM cells and a second array of CAM cells. A first plurality of compare signal lines is coupled to the first array CAM cells and a second plurality of compare signal lines coupled to the second array of CAM cells. A plurality of storage elements have inputs coupled to the first plurality of compare signal lines and outputs coupled to the second plurality of compare signal lines.

Abstract: A content addressable memory (CAM) cell. The CAM cell includes a first and second memory cells and a diffusion region. First and second transistors are formed adjacent one another in the diffusion region and coupled to the first memory cell, and third and fourth transistors are formed adjacent one another in the diffusion region and coupled to the second memory cell.

Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.

Abstract: A content addressable memory (CAM) architecture. In one embodiment, the CAM architecture includes a CAM array including a plurality of rows of CAM cells to compare, in a first compare operation, comparand data with data stored in the rows and output match results on a plurality of match signal lines; a timed storage circuit having data inputs coupled to the match signal lines and an enable input; and a dynamic timing generator circuit including a first compare circuit to perform a second compare operation to generate an enable signal coupled to the enable input to enable the timed storage circuit to capture the match results.

Abstract: A method and apparatus for loading comparand data into a content addressable memory system. For one embodiment, the CAM system includes a CAM array, a comparand register and select logic. The CAM array includes a plurality of rows of CAM cells each segmented into a plurality of row segments each having a plurality of CAM cells. The comparand register includes a plurality of segments for storing comparand data for comparing with data stored in the CAM array. The select logic selectively enables each segment of the comparand register to store a portion of the comparand data in response to configuration information. The configuration information is indicative of the width and depth of the CAM array. The select logic may also enable each segment of the comparand register to simultaneously load the comparand data.

Abstract: A match line control circuit includes a match line control circuit coupled between a match line of a row of an associated CAM and a supply voltage. The match line control circuit adjusts the charge current for the match line in response to a valid bit and a pre-charge signal. For some embodiments, the match line control circuit includes a dynamic component and a static component to control the match line.