Abstract: A content addressable memory (CAM) device that includes a plurality of CAM cells coupled to a match line to affect a voltage of the match line in response to data values of the CAM cells and comparand data being in a predetermined logical relationship, and a match detect circuit coupled to the match line and adapted to differentially compare the voltage of the match line with a fixed reference voltage and, in response, generate an output signal having two or more logical states corresponding to the states of the predetermined logical relationship between the data value and the comparand data.

Abstract: A ternary content addressable memory device. The device includes a ternary CAM array segmented into a plurality of array groups, each of which includes a number of rows of ternary CAM cells. Each array group is assigned to a particular priority by storing the priority number for each array group in an associated storage element. Data entries are then stored in array groups according to priority.

Abstract: A CAM device for comparing a search key with a plurality of CAM words stored in a main CAM array includes a pre-compare CAM array and match line control logic. The pre-compare CAM array includes a plurality of rows, each for storing a set of pre-compare bits generated by performing a logical function on a corresponding CAM word. The match line control logic selectively pre-charges match lines in the main CAM array in response to match results from a pre-compare operation between an encoded search key and corresponding sets of pre-compare bits.

Abstract: A content addressable memory (CAM) device having a cascaded CAM array. The cascaded CAM array includes a first array of CAM cells and a second array of CAM cells. A first plurality of compare signal lines is coupled to the first array CAM cells and a second plurality of compare signal lines coupled to the second array of CAM cells. A plurality of storage elements have inputs coupled to the first plurality of compare signal lines and outputs coupled to the second plurality of compare signal lines.

Abstract: A content addressable memory (CAM) device having circuitry to generate a biased sequence of addresses. A first counter circuit increments an address value in response to a clock signal and resets the address value to a start address in response to a control signal. A second counter increments a limit value in response to a control signal. A compare circuit compares the address value and the limit value and, if the address value and the limit value have a predetermined relationship, asserts the control signal.

Abstract: A content addressable memory (CAM) device having a range compare function. A boundary value is stored within a plurality of CAM cells within the CAM device. A range compare operation is performed to determine whether a comparand is greater than the boundary value. A result signal is asserted if the comparand is greater than the boundary value.

Abstract: A content addressable memory (CAM) device including a plurality of CAM cells, a pair of bit lines and a sense amplifier. Each of the plurality of CAM cells includes a static storage circuit to store a data value and is coupled to the pair of bit lines. The sense amplifier includes a first transistor having first and second terminals coupled to first and second bit lines of the pair of bit lines, respectively.

Abstract: A content addressable memory (CAM) having a main array including a plurality of columns of CAM cells, a spare column of CAM cells selectable to functionally replace a defective column of CAM cells in the main array, and circuitry to shift data corresponding to the defective column and data corresponding to all subsequent columns to corresponding adjacent non-defective columns.

Abstract: According to one embodiment of the present invention, the CAM device includes a CAM array that includes a plurality of rows of CAM cells each coupled to a match line, a priority encoder coupled to the match lines to generate an index, a counter and compare logic coupled to the counter and the priority encoder to compare the index and a counter value from the counter.

Abstract: A content addressable memory (CAM) device having a simultaneous write and compare function. The CAM device includes a plurality of rows of CAM cells, and match lines and word lines coupled to the rows of CAM cells. The CAM device further includes a plurality of switching circuits coupled to the word lines and the match lines, each switching circuit being adapted to selectively disable assertion of a match signal on a corresponding one of the match lines based, at least in part, on the state of a corresponding one of the word lines.

Abstract: An apparatus and method for generating a comparand in a content addressable memory array. The apparatus includes a content addressable memory (CAM) array and translation circuitry to receive translation information indicative of translation of a bit group from an initial position in input data to a different position in a comparand transmitted to the CAM array. The translation circuitry includes a switch circuit, one or more storage elements to store the translation information, and one or more decode circuitry to decode the translation information and establish switch circuit connections between the initial position and the position in the comparand. The apparatus also includes program circuitry to provide a bit level programming interface with the translation circuitry. The apparatus may also include a programming bit register to store programming information in the form of a binary pattern where each bit represents a bit group of the input data.

Abstract: A content addressable memory (CAM) device having an error correction function. The CAM device includes an array of CAM cells, row parity storage elements and column parity storage elements. The row parity storage elements store row parity values that correspond to contents of respective rows of the CAM cells, and the column parity storage elements store column parity values that correspond to respective columns of the CAM cells. A bit error in the array is detected through row and column parity checking that uniquely identifies the row and column location of the error and enables correction of the error.

Abstract: A method and apparatus are described for the filtering of a common input string to generate various filtered comparand strings. The filtering of a common input string enables concurrent lookups in different tables to be performed on multiple filtered comparands by different CAM devices (or different blocks within a CAM device), to compare the data in the filtered comparand strings with data stored in its associative memory. By performing multiple lookups in parallel, rather than sequentially, packet throughput in a CAM may be significantly increased.

Abstract: A CAM device to perform in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction; (3) perform the comparison of the comparand data with a first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

Abstract: A content addressable memory (CAM) device comprising a plurality of CAM blocks and a block control circuit. The plurality of CAM blocks each includes an array of CAM cells to store data words and an array of priority number storage circuits to store priority numbers. Each priority number indicates a priority of a respective one of the data words relative to others of the data words. The block control circuit has an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each select signal selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to the class code.

Abstract: A content addressable memory (CAM) device with mode-selectable match detect timing. The CAM device includes a plurality of rows of CAM cells coupled to respective match lines. Storage circuits are coupled to the match lines and configured to store match indications signaled thereon in response to assertion of a first timing signal. A timing control circuit is coupled to the storage circuits and configured to assert the first timing signal at either a first instant or a second instant according to the state of a mode select signal.

Abstract: A semiconductor package with solder bumps and a method for making the same are described. One embodiment comprises a flip-chip design with a rectangular semiconductor die with a relatively large aspect ratio bonded to a substantially square substrate through solder bumps. In one embodiment, active bumps are concentrated in an area relatively close to the neutral point of the die, for example, in a substantially square area about the neutral point.

Abstract: An apparatus having an output register coupled to a content addressable memory (CAM) array. The output register may be configured to output data based on a delayed clock signal. A programmable delay circuit may be coupled to receive a reference clock signal and generate the delayed clock signal using one or more delay elements.

Abstract: A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.

Abstract: A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.