Patents Assigned to NetLogic Microsystems, Inc.
  • Synchronous content addressable memory
    Patent number: 6961810
    Abstract: A CAM device to perform in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction; (3) perform the comparison of the comparand data with a first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: November 1, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Bindiganavale S. Nataraj, Sandeep Khanna
  • Content addressable memory with mode-selectable match detect timing
    Patent number: 6944039
    Abstract: A content addressable memory (CAM) device with mode-selectable match detect timing. The CAM device includes a plurality of rows of CAM cells coupled to respective match lines. Storage circuits are coupled to the match lines and configured to store match indications signaled thereon in response to assertion of a first timing signal. A timing control circuit is coupled to the storage circuits and configured to assert the first timing signal at either a first instant or a second instant according to the state of a mode select signal.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: September 13, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Bindiganavale S. Nataraj, Sandeep Khanna, Varadarajan Srinivasan
  • Method for fabricating integrated circuit package with solder bumps
    Patent number: 6943060
    Abstract: A semiconductor package with solder bumps and a method for making the same are described. One embodiment comprises a flip-chip design with a rectangular semiconductor die with a relatively large aspect ratio bonded to a substantially square substrate through solder bumps. In one embodiment, active bumps are concentrated in an area relatively close to the neutral point of the die, for example, in a substantially square area about the neutral point.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: September 13, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Kollengode Subramanian Narayanan
  • Content addressable memory with block-programmable mask write mode, word width and priority
    Patent number: 6944709
    Abstract: A content addressable memory (CAM) device comprising a plurality of CAM blocks and a block control circuit. The plurality of CAM blocks each includes an array of CAM cells to store data words and an array of priority number storage circuits to store priority numbers. Each priority number indicates a priority of a respective one of the data words relative to others of the data words. The block control circuit has an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each select signal selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to the class code.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: September 13, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Bindiganavale S. Nataraj, Nilesh A. Gharia, Rupesh R. Roy, Jose P. Pereira, Varadarajan Srinivasan, Sandeep Khanna, Hok F. Wong
  • Programmable delay circuit within a content addressable memory
    Patent number: 6944040
    Abstract: An apparatus having an output register coupled to a content addressable memory (CAM) array. The output register may be configured to output data based on a delayed clock signal. A programmable delay circuit may be coupled to receive a reference clock signal and generate the delayed clock signal using one or more delay elements.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: September 13, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Sandeep Khanna
  • Content addressable memory with programmable word width and programmable priority
    Patent number: 6934795
    Abstract: A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: August 23, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Bindiganavale S. Nataraj, Nilesh A. Gharia, Rupesh R. Roy, Jose P. Pereira, Varadarajan Srinivasan, Sandeep Khanna, Hok F. Wong
  • Content addressable memory with hashing function
    Patent number: 6934796
    Abstract: A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: August 23, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Jose P. Pereira, Sunder R. Rathnavelu, Rodolfo G. Beraha, Lewis M. Carroll, Ronald S. Jankov
  • Content addressable memory with selective error logging
    Patent number: 6914795
    Abstract: A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapted to generate an error indication according to whether the data value includes an error. An error storage circuit is couple to receive the error indication from the error detection circuit and is adapted to store an error address that corresponds to the selected storage location if the error indication indicates that the data value includes an error and if the error address is not already stored within the error storage circuit.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: July 5, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Sandeep Khanna
  • Classless interdomain routing using binary content addressable memory
    Patent number: 6910097
    Abstract: A method and apparatus for using a binary CAM array to implement Classless Interdomain Routing (CIDR) address processing. A binary CAM array is segmented into a plurality of array groups, each of which includes a number of rows of binary CAM cells and an associated group global mask. Each array group may be assigned to a particular prefix length by storing a prefix mask pattern corresponding to the prefix length in the array group's associated group global mask. CIDR address entries are then stored in array groups assigned to corresponding CIDR prefixes so that an array group assigned to a particular prefix stores only CIDR addresses having that prefix.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: June 21, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Bindiganavale S. Nataraj, Sandeep Khanna
  • Bit line control circuit for a content addressable memory
    Patent number: 6906937
    Abstract: A bit line control circuit is coupled between a bit line of an associated Content Addressable Memory (CAM). Array and a supply voltage. The bit line control circuit adjusts the charge current for the bit line in response to a bit line control signal. For some embodiments, the bit line control circuit includes a dynamic component and a static component to control the bit line.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: June 14, 2005
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Bindiganavale S. Nataraj
  • Content addressable memory with cascaded array
    Patent number: 6903953
    Abstract: A content addressable memory (CAM) device having a cascaded CAM array. The cascaded CAM array includes a first array of CAM cells and a second array of CAM cells. A first plurality of compare signal lines is coupled to the first array CAM cells and a second plurality of compare signal lines coupled to the second array of CAM cells. A plurality of storage elements have inputs coupled to the first plurality of compare signal lines and outputs coupled to the second plurality of compare signal lines.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: June 7, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Sandeep Khanna
  • Content addressable memory having dynamic match resolution
    Patent number: 6898099
    Abstract: A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a corresponding CAM cell in each of the plurality of rows of CAM cells, a plurality of timed storage circuits, each having a data input coupled to a corresponding match line and having an enable input coupled to an enable signal line, a timing generator configured to generate an enable signal on the enable signal line, and a plurality of load elements.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: May 24, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Bindiganavale S. Nataraj, Sandeep Khanna
  • Method and apparatus for determining a longest prefix match in a content addressable memory device
    Patent number: 6892272
    Abstract: A method and apparatus for determining a longest prefix match in a content addressable memory (CAM) device is described. The CAM device includes a CAM array that may be arbitrarily loaded with CIDR addresses that are not prearranged prior to their entry into the CAM device. For one embodiment, the CAM array is a ternary CAM array that includes CAM cells storing CAM data, mask cells storing prefix mask data for the corresponding CAM cells, a CAM match line for indicating a match between a search key and the CAM data (as masked by the prefix mask data), prefix match lines, and prefix logic circuits for comparing the CAM match line with the prefix mask data. The prefix logic circuits determine the longest prefix among the CAM locations that match the search key, regardless of where the matching locations are logically located in the CAM array.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: May 10, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Ramagopal Madamala
  • Block-writable content addressable memory device
    Patent number: 6876559
    Abstract: A content addressable memory device including a memory to store a searchable database, a search circuit, and a first-in-first-out storage circuit. The search circuit generates a plurality of address values that correspond to unoccupied storage locations within the memory, and the plurality of address values are queued within the first-in-first-out storage circuit to enable the address values to be read in succession by an external device.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: April 5, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Sunder R. Rathnavelu, David W. Ng, Jose P. Pereira
  • Auto read content addressable memory cell and array
    Patent number: 6867989
    Abstract: A content addressable memory (CAM) cell including a memory cell coupled to a word line, a compare circuit coupled to the memory cell and to a match line, and a driver circuit having an input coupled to the match line and an output coupled to the word line.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: March 15, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Rupesh Roy
  • Row redundancy in a content addressable memory device
    Patent number: 6865098
    Abstract: A content addressable memory (CAM) has a main array including a plurality of rows of CAM cells, one or more spare rows of CAM cells selectable to functionally replace defective rows of CAM cells in the main array, and a control circuit for disabling the defective rows by writing predetermined data to the defective rows of CAM cells.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: March 8, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Michael Edwin Ichiriu, Masaru Shinohara, YueFei Ge, Lan Lee
  • Multi-chip module having content addressable memory
    Patent number: 6864122
    Abstract: A monolithic Multi-chip Module (MCM) package includes two or more individual CAM dice mounted on a substrate formed as, for example, a plastic ball grid array (PBGA) package. The substrate includes an interconnect structure to route signals between corresponding pads of the CAM dice and balls of the MCM package. In some embodiments, the footprint of the MCM ball grid array package is identical to the footprint of a similar PBGA package housing a single CAM die. Each CAM die within the MCM package may be assigned the same device identification number (DID).
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: March 8, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Charles C. Huse, William G. Nurge, Varadarajan Srinivasan
  • Programmable delay circuit within a content addressable memory
    Patent number: 6865121
    Abstract: An apparatus including a content addressable memory (CAM) array, a clocked circuit coupled to the CAM array, and a programmable delay circuit coupled to receive a reference clock signal and generate a programmable delayed clock signal using a delay element for the clocked circuit. The CAM array may include a plurality of rows of CAM cells each having a corresponding match line for carrying a match signal indicative of whether comparand data matches data of the corresponding row of CAM cells.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: March 8, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Sandeep Khanna
  • Multi-compare content addressable memory cell
    Patent number: 6856527
    Abstract: A method and apparatus for simultaneously performing a plurality of compare operations in a content addressable memory (CAM) device. For one embodiment, the CAM device includes first and second memory cells to store first and second data, and first and second compare circuits coupled respectively to first and second match lines. The first compare circuit has a first input coupled to the first memory cell, a plurality of second inputs to receive first comparand data, and a third input coupled to the second memory cell. The second compare circuit has a first input coupled to the first memory cell, a plurality of second inputs to receive second comparand data; and a third input coupled to the second memory cell.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: February 15, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Jose P. Pereira, Nilesh A. Gharia
  • Word line driver circuit for a content addressable memory
    Patent number: 6845025
    Abstract: A word line driver circuit is coupled to a word line of an associated Content Addressable Memory (CAM) array. The word line driver circuit adjusts the word line read voltage in response to a compare signal indicative of whether the CAM array is performing a concurrent compare operation. For some embodiments, the word line driver circuit selectively provides a relatively high word line read voltage or a relatively low word line read voltage in response to the compare signal.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: January 18, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Bindiganavale S. Nataraj