Abstract: A match line control circuit includes a match line control circuit coupled between a match line of a row of an associated CAM and a supply voltage. The match line control circuit adjusts the charge current for the match line in response to a valid bit and a pre-charge signal. For some embodiments, the match line control circuit includes a dynamic component and a static component to control the match line.

Abstract: A CAM system having intra-row configurability. For one embodiment, the CAM system includes a CAM array having a number of rows of CAM cells each segmented into row segments. Each row segment includes a number of CAM cells coupled to a corresponding match line segment. Individual row segments or groups of row segments are uniquely addressable by address logic in response to configuration information that indicates a width and depth configuration of the CAM array. The configuration information may be stored in a configuration register. Data may be communicated with an addressed row segment or group of row segments using data access circuitry. Priority encoding circuitry may be included to generate the address of a row segment or group of row segments that stores data matching comparand data in response to the configuration information.

Abstract: A method and apparatus for detecting a match in an intra-row configurable CAM system. For one embodiment, the CAM system includes a CAM array and match flag logic. The CAM array includes a plurality of rows of CAM cells each segmented into a plurality of row segments having a plurality of CAM cells coupled to a corresponding match line segment. The match flag logic is coupled to the match line segments and determines when first comparand data matches data stored in at least one of the row segments in response to first configuration information, and determines when second comparand data matches data stored in at least one group of row segments in response to second configuration information. The first configuration information is indicative of a first width and depth configuration of the CAM array, and the second configuration information is indicative of a second width and depth configuration of the CAM array.

Abstract: A method and apparatus for determining a match address in an intra-row configurable CAM system. For one embodiment, the CAM system includes a CAM array and priority encoding circuitry. The CAM system includes a plurality of rows of CAM cells each segmented into a plurality of row segments having a plurality of CAM cells coupled to a corresponding match line segment. The priority encoding circuitry is coupled to the match line segments and has inputs to receive configuration information indicative of a width and depth configuration of the CAM array. The priority encoding circuitry is configured to generate a first match address in the CAM array corresponding to a row segment that stores data matching first comparand data in response to first configuration information, and is further configured to generate a second match address in the CAM array corresponding to a group of row segments that store data matching second comparand data in response to the second configuration information.

Abstract: A CAM device having plurality of CAM blocks includes circuitry to disable one or more defective CAM blocks, and to selectively translate address space in the disabled CAM blocks to the remaining enabled CAM blocks. In one embodiment, each CAM block is coupled to a corresponding block select circuit and to an address translation circuit. Each block select circuit provides a select signal to a corresponding CAM block to selectively enable or disable the CAM block. The address translation circuit includes logic that translates address space from disabled (e.g., defective) CAM blocks to enabled (e.g., non-defective) CAM blocks. During read and write operations, an address to access a row in a first of the CAM blocks is received into the address translation logic. If the first CAM block is disabled, the address translation logic translates the address to access a row in a second of the CAM blocks.

Abstract: A ternary content addressable memory (CAM) cell includes a dynamic random access memory (DRAM) cell storing data values and a DRAM cell storing mask values. The mask values control a masking circuit. The CAM cell also includes a compare circuit coupled among the DRAM cell and the masking circuit. The compare circuit of an embodiment receives data and comparand data and affects a logical state of a match line in response to a predetermined relationship between the data and comparand data. The compare circuit includes a first pair of transistors coupled for conduction state control by the comparand data and a second pair of transistors coupled for conduction state control by the data. The first pair of transistors includes two n-channel transistors. The second pair of transistors includes one n-channel and one p-channel transistor. A sense amplifier couples to the match line to detect changes in match line logical state.

Abstract: A content addressable memory (CAM) that includes a CAM array and a write circuit. The write circuit is coupled the CAM array and has a coding circuit to convert a first value into a second value, and a select circuit to select either the first value or the second value to be stored in the CAM array.

Abstract: A semiconductor package with solder bumps and a method for making the same are described. One embodiment comprises a flip-chip design with a rectangular semiconductor die with a relatively large aspect ratio bonded to a substantially square substrate through solder bumps. In one embodiment, active bumps are concentrated in an area relatively close to the neutral point of the die, for example, in a substantially square area about the neutral point.

Abstract: A method and apparatus for detecting a multiple match in an intra-row configurable CAM system. For one embodiment, the CAM system includes a CAM array and multiple match flag logic. The CAM system has a plurality of rows of CAM cells each row segmented into a plurality of row segments having a plurality of CAM cells coupled to a corresponding match line segment. The multiple match flag logic is coupled to the match line segments and determines when first comparand data matches data stored in each of two or more row segments in response to first configuration information, and determines when second comparand data matches data stored in each of two or more groups of row segments in response to second configuration information. The first configuration information is indicative of a first width and depth configuration of the CAM array, and the second configuration information is indicative of a second width and depth configuration of the CAM array.

Abstract: A method and apparatus are described for the filtering of a common input string to generate various filtered comparand strings. The filtering of a common input string enables concurrent lookups in different tables to be performed on multiple filtered comparands by different CAM devices (or different blocks within a CAM device), to compare the data in the filtered comparand strings with data stored in its associative memory. By performing multiple lookups in parallel, rather than sequentially, packet throughput in a CAM may be significantly increased.

Abstract: A content addressable memory (CAM) device having a data CAM array and an error CAM array. The data CAM array is provided to store data words, compare the data words with a comparand value, and, if one of the data words matches the comparand value, assert a match signal that corresponds to the matching data word. A priority encoder responds to the match signal by outputting a match address that corresponds to the matching data word. The error CAM array is provided to store at least one error address value and is coupled to the priority encoder to receive the match address. The error CAM array compares the match address with the error address value and asserts a match error signal if the match address matches the error address value.

Abstract: A CAM system includes two or more CAM devices having the same device identification number (DID). One or more priority address bits indicating priority between the CAM devices may be assigned to each CAM device. Each CAM device may receive a mode signal indicating whether the CAM device operates independently or in cooperation with other cascaded CAM devices. During compare operations, each CAM device generates a highest priority match (HPM) index. A selected number of the priority address bits are inserted between the DID and the HPM index to form a device index for the system. During read and write operations, a first portion of an input address is used to select a row of CAM cells in each CAM device. A second portion of the input address is compared to a selected number of the priority address bits to enable an array in one of the CAM devices.

Abstract: A plurality of match and priority encoding logic (MPL) circuits are connected in a chain. Each MPL circuit includes a plurality of input terminals coupled to an associated set of match lines from a content addressable memory (CAM) array, an index input port to receive an input index from a previous MPL circuit, an index output port to provide an output index to a next MPL circuit, and a select terminal to receive a select signal.

Abstract: A content addressable memory (CAM) having a main array including a plurality of columns of CAM cells, a spare column of CAM cells selectable to functionally replace a defective column of CAM cells in the main array, a steering circuit for steering data corresponding to the defective column to the spare column, and a global mask circuit for masking the defective column during a compare operation.

Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.

Abstract: A content addressable memory (CAM) device having a simultaneous write and compare function. The CAM device includes a plurality of rows of CAM cells, and match lines and word lines coupled to the rows of CAM cells. The CAM device further includes a plurality of switching circuits coupled to the word lines and the match lines, each switching circuit being adapted to selectively disable assertion of a match signal on a corresponding one of the match lines based, at least in part, on the state of a corresponding one of the word lines.

Abstract: Entry relocation in a content addressable memory (CAM) device. The CAM device is instructed to store a first value and to supply an address at which the first value is stored. If the address indicates that the first value has been stored within an overflow storage array of the CAM device, the CAM device is instructed to store the first value again.

Abstract: A content addressable memory (CAM) device having a data CAM array and an error CAM array. The data CAM array is provided to store data words, compare the data words with a comparand value, and, if one of the data words matches the comparand value, assert a match signal that corresponds to the matching data word. A priority encoder responds to the match signal by outputting a match address that corresponds to the matching data word. The error CAM array is provided to store at least one error address value and is coupled to the priority encoder to receive the match address. The error CAM array compares the match address with the error address value and asserts a match error signal if the match address matches the error address value.

Abstract: A content addressable memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare the comparand data with a first group of CAM cells in a CAM array; (3) perform the comparison of the comparand data with the first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

Abstract: A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.