Abstract: A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapted to generate an error indication according to whether the data value includes an error. An error storage circuit is coupled to receive the error indication from the error detection circuit and is adapted to store an error address that corresponds to the selected storage location if the error indication indicates that the data value includes an error and if the error address is not already stored within the error storage circuit.

Abstract: A method and apparatus that may be used to disable one or more defective CAM blocks, and to selectively re-assign priority between the remaining enabled CAM blocks. In one embodiment, each CAM block includes an array of CAM cells organized in a number of rows and columns, where each row has a match line to indicate match conditions therein during a compare operation. Each block also includes a block priority encoder coupled to the number of match lines and having an output to provide a row index of a row that stores data that matches comparand data. The row indexes from the CAM blocks are provided to a main priority encoder that stores a dynamic block index for each of the plurality of CAM blocks. The main priority encoder combines each row index with a corresponding block index to generate a device index for each CAM block. The main priority encoder may re-assign priority between the plurality of CAM blocks by manipulating the dynamic block indexes.

Abstract: A content address memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare the comparand data with a first group of CAM cells in a CAM array; (3) perform the comparison of the comparand data with the first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

Abstract: A content addressable memory (CAM) architecture. In one embodiment, the CAM architecture includes a CAM array including a plurality of rows of CAM cells to compare, in a first compare operation, comparand data with data stored in the rows and output match results on a plurality of match signal lines; a timed storage circuit having data inputs coupled to the match signal lines and an enable input; and a dynamic timing generator circuit including a first compare circuit to perform a second compare operation to generate an enable signal coupled to the enable input to enable the timed storage circuit to capture the match results.

Abstract: An apparatus having an output register coupled to a content addressable memory (CAM) array. The output register may be configured to output data based on a delayed clock signal. A programmable delay circuit may be coupled to receive a reference clock signal and generate the delayed clock signal using one or more delay elements.

Abstract: A content addressable memory (CAM) device having a data CAM array and an error CAM array. The data CAM array is provided to store data words, compare the data words with a comparand value, and, if one of the data words matches the comparand value, assert a match signal that corresponds to the matching data word. A priority encoder responds to the match signal by outputting a match address that corresponds to the matching data word. The error CAM array is provided to store at least one error address value and is coupled to the priority encoder to receive the match address. The error CAM array compares the match address with the error address value and asserts a match error signal if the match address matches the error address value.

Abstract: A method and apparatus for determining the address of a highest priority matching entry in a segmented content addressable memory device. For one embodiment, a segmented CAM device is disclosed that includes m CAM array blocks each having n rows of CAM cells coupled to one of n corresponding match lines. The CAM array blocks have a predetermined priority based on their addresses such that the first CAM array block has the highest priority addresses and the mth CAM array block has the lowest priority addresses. Comparand data is provided for comparison with entries in each of the CAM array blocks. Each row of CAM cells in each block has a row enable logic circuit. A main priority encoder is coupled to the row enable logic circuits of the mth CAM array block. Each CAM array block also has an associated match flag circuit to determine a match flag signal for the block. A block priority encoder encodes the match flag signals into a block address of the highest priority matching location.

Abstract: A method and apparatus for determining an exact match in a ternary CAM device. Each ternary CAM cell includes CAM cells for storing CAM data, local mask cells for storing prefix mask data for the corresponding CAM cells, and a mask override circuit. Each local mask cell includes a masking circuit that masks the prefix mask data or CAM data provided to the comparison circuit, or masks the comparison result from the match line of a CAM cell. The mask override circuit effectively overrides the prefix mask data stored in the local mask cell. The mask override circuit performs the override function by negating the operation of the mask circuit such that no masking operation occurs when an exact match compare or invalidate function is performed by the ternary CAM device. For example, during an exact match operation, the CAM cells compare comparand data with unmasked CAM data and provide the compare results to CAM match lines.

Abstract: A multi-counter based system having a counter array. Each counter of the array having a memory cell. The system also includes an address decoder coupled to the counter array to select at least one of the memory cells within the counter array and read/write circuitry coupled to the counter array to pass data with the counter array.

Abstract: A content address memory (CAM) device that implements a read text highest priority or “RNHPM” instruction. The CAM device initially searches its CAM locations for a match with comparand data. If multiple matches are identified, then the CAM device initially outputs the highest priority matching address. The CAM device may output the highest priority matching address in the same system or a later clock cycle in which the compare instruction was provided. The CAM device may also output data stored in one or more of the CAM cells located at the highest priority matching location and/or status information including the match flags, a full flag, validity bits (e.g., skip and empty bits), and other status information. An RNHPM instruction may then be provided to the CAM device in the next clock cycle or a later clock cycle and cause the next highest priority matching address to be output by the CAM device.

Abstract: An inter-row configurable content addressable memory (CAM) system. For one embodiment, the CAM system includes an array of CAM cells having a plurality of rows of CAM cells for storing a data word chain, wherein the data word chain comprises a sequence of at least two data words each stored in a different row of CAM cells, and wherein each row of CAM cells includes a first group of CAM cells for storing a pointer and a second group of CAM cells for storing one of the data words. The pointer of the first data word of the data word chain may be a predetermined number greater than the number of rows in the CAM array. The pointers associated with the other data words of the data word chain each store an address of the previous data word in the data word chain. The CAM system further includes a write circuit for writing the data words into the rows of CAM cells, an address decoder coupled to the CAM array, and a priority encoder coupled to the CAM array.

Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.

Abstract: A method and apparatus for determining an exact match in a ternary CAM device. Each ternary CAM cell includes CAM cells for storing CAM data, local mask cells for storing prefix mask data for the corresponding CAM cells, and a mask override circuit. Each local mask cell includes a masking circuit that masks the prefix mask data or CAM data provided to the comparison circuit, or masks the comparison result from the match line of a CAM cell. The mask override circuit effectively overrides the prefix mask data stored in the local mask cell. The mask override circuit performs the override function by negating the operation of the mask circuit such that no masking operation occurs when an exact match compare or invalidate function is performed by the ternary CAM device. For example, during an exact match operation, the CAM cells compare comparand data with unmasked CAM data and provide the compare results to CAM match lines.

Abstract: A monolithic Multi-chip Module (MCM) package includes two or more individual CAM dice mounted on a substrate formed as, for example, a plastic ball grid array (PBGA) package. The substrate includes an interconnect structure to route signals between corresponding pads of the CAM dice and balls of the MCM package. In some embodiments, the footprint of the MCM ball grid array package is identical to the footprint of a similar PBGA package housing a single CAM die. Each CAM die within the MCM package may be assigned the same device identification number (DID).

Abstract: A method and apparatus for determining an exact match in a ternary CAM device. Each ternary CAM cell includes CAM cells for storing CAM data, local mask cells for storing prefix mask data for the corresponding CAM cells, and a mask override circuit. Each local mask cell includes a masking circuit that masks the prefix mask data or CAM data provided to the comparison circuit, or masks the comparison result from the match line of a CAM cell. The mask override circuit effectively overrides the prefix mask data stored in the local mask cell. The mask override circuit performs the override function by negating the operation of the mask circuit such that no masking operation occurs when an exact match compare or invalidate function is performed by the ternary CAM device. For example, during an exact match operation, the CAM cells compare comparand data with unmasked CAM data and provide the compare results to CAM match lines.

Abstract: A method and apparatus for determining a longest prefix match in a segmented content addressable memory (CAM) device. The CAM device includes multiple CAM array blocks that each may be arbitrarily loaded with CIDR addresses. For one embodiment, each CAM array is a ternary CAM array that includes CAM cells storing CAM data, mask cells storing prefix mask data for the corresponding CAM cells, a CAM match line for indicating a match between a search key and the CAM data (as masked by the prefix mask data), and prefix logic circuits for comparing the logical state of the CAM match line with the prefix mask data. The prefix logic circuits determine the longest prefix in each CAM array block from among CAM entries that match the search key. The longest prefixes from each block are provided to compare circuitry that determines which of the longest prefixes is the longest for the entire CAM device.

Abstract: A content addressable memory (CAM) device having an array including a plurality of rows of CAM cells each coupled to a match line; match flag logic having inputs coupled to the match line, and having an output to provide an internal match flag signal indicative of match conditions between a comparand word and data stored in the array; a plurality of match flag inputs to receive input match information from one or more other CAM devices; a match flag output to provide output match information to one or more other CAM devices; and cascade logic coupled to the plurality of match flag inputs and the match flag output for selecting which input match information received from the match flag inputs is logically combined with the internal match flag to generate the output match information.

Abstract: Match lines of a CAM array are grouped into sets and provided to corresponding match and priority encoding logic (MPL) circuits. Each MPL circuit includes an input connected to an output of a previous MPL circuit. The last MPL circuit has an output connected to a control circuit. In response to the set of match signals, each MPL circuit generates a match flag and the index of the highest priority match for the set. In response to the match flags, the control circuit provides a plurality of select signals to corresponding MPL circuits each of which, in response to its select signal, provides either the set index generated therein or a set index received from the previous MPL circuit to the next MPL circuit. The select signals are asserted so that the index of the highest priority match line set ripples through the MPL circuits to the control circuit.

Abstract: A content address memory (CAM) device that implements a read next highest priority or “RNHPM” instruction. The CAM device initially searches its CAM locations for a match with comparand data. If multiple matches are identified, then the CAM device initially outputs the highest priority matching address. The CAM device may output the highest priority matching address in the same system or clock cycle in which the compare instruction was provided. The CAM device may also output data stored in one or more of the CAM cells located at the highest priority matching location and/or status information including the match flags, a full flag, validity bits (e.g., skip and empty bits), and other status information. An RNHPM instruction may then be provided to the CAM device in the next clock cycle or a later clock cycle and cause the next highest priority matching address to be output by the CAM device.

Abstract: A CAM device that allows defective rows in one CAM block to be functionally replaced by spare rows from any CAM block in the device. In some embodiments, the CAM device includes a main address decoder, a plurality of CAM blocks, a corresponding plurality of spare address decoders, and a block select circuit. In one embodiment, each CAM block includes a main CAM array having a plurality of rows of CAM cells each coupled to a corresponding word line, and a spare row of CAM cells coupled to a spare word line. Each spare row may be used to functionally replace a defective row in the same CAM block or in any other CAM block by programming the address of the defective row into the corresponding spare address decoder.